diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2020-07-13 15:57:52 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-07-16 17:11:29 +0000 |
| commit | d45835837985c4e97b55d09a42a2297da714d891 (patch) | |
| tree | e95ff367f9e514ff79a8a8dfa03ea5090ab1a77a /src/soc | |
| parent | b20a16ef4ecc841a23c9753df4317b65101ce0e9 (diff) | |
soc/amd/picasso,mb/{zork,mandolin}: Remove invalid UPWS variable
PMx0EE is not defined in the Picasso PPR.
BUG=b:153001807, b:154756391
TEST=None
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I98caf0cd2d0bdcf19de2b945dcf74f5cf7354769
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/picasso/acpi/pcie.asl | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/amd/picasso/acpi/pcie.asl b/src/soc/amd/picasso/acpi/pcie.asl index e88026781d..cb4be7fcaf 100644 --- a/src/soc/amd/picasso/acpi/pcie.asl +++ b/src/soc/amd/picasso/acpi/pcie.asl @@ -74,8 +74,6 @@ IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { Offset(0x60), /* AcpiPm1EvgBlk */ P1EB, 16, - Offset(0xee), - UPWS, 3, } OperationRegion (P1E0, SystemIO, P1EB, 0x04) Field (P1E0, ByteAcc, Nolock, Preserve) { |