diff options
| author | Maxim Polyakov <max.senia.poliak@gmail.com> | 2019-08-23 15:22:21 +0300 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-08-30 10:39:49 +0000 |
| commit | c6f2b6135596c43f4bf467f7b6372b0ad3927e2c (patch) | |
| tree | 4e1490c1daf7e370e34888e8b8e4945144f4955f /src/soc | |
| parent | a0cd4b18afc82b5a3308ed80cd06c5dfbc5bd193 (diff) | |
soc/intel/skl/acpi: add description for missing PCIe ports
According to the documentation, Sunrise PCH-H [1,2] and Lewisburg PCH
[3] supports up to 16 PCIe ports. However, ACPI contains a description
for only 12 ports. This patch adds ACPI code for missing ports
[1] page 182, Intel (R) 100 Series and Intel (R) C230 Series PCH
Family Platform Controller Hub (PCH), Datasheet, Vol 1 of 2,
December 2018, Document Number: 332690-005EN
[2] page 180, Intel (R) 200 Series and Intel (R) Z370 Series PCH
Family Platform Controller Hub (PCH), Datasheet, Vol 1 of 2,
October 2017, Document Number: 335192-003
[3] page 39, Intel(R) C620 Series Chipset Platform Controller Hub
(PCH) Datasheet, May 2019. Document Number: 336067-007US
Change-Id: I954870136e0c8e5ff5d7ff623c7a6432b829abaf
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/skylake/acpi.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/skylake/acpi/pcie.asl | 76 |
2 files changed, 76 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index aa51cbe7a5..ccfc7b79df 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -805,6 +805,10 @@ const char *soc_acpi_name(const struct device *dev) case PCH_DEVFN_PCIE10: return "RP10"; case PCH_DEVFN_PCIE11: return "RP11"; case PCH_DEVFN_PCIE12: return "RP12"; + case PCH_DEVFN_PCIE13: return "RP13"; + case PCH_DEVFN_PCIE14: return "RP14"; + case PCH_DEVFN_PCIE15: return "RP15"; + case PCH_DEVFN_PCIE16: return "RP16"; case PCH_DEVFN_UART0: return "UAR0"; case PCH_DEVFN_UART1: return "UAR1"; case PCH_DEVFN_GSPI0: return "SPI0"; diff --git a/src/soc/intel/skylake/acpi/pcie.asl b/src/soc/intel/skylake/acpi/pcie.asl index 84cb4370b6..b039f539ee 100644 --- a/src/soc/intel/skylake/acpi/pcie.asl +++ b/src/soc/intel/skylake/acpi/pcie.asl @@ -69,7 +69,7 @@ Method (IRQM, 1, Serialized) { Switch (ToInteger (Arg0)) { - Case (Package () { 1, 5, 9 }) { + Case (Package () { 1, 5, 9, 13 }) { If (PICM) { Return (IQAA) } Else { @@ -77,7 +77,7 @@ Method (IRQM, 1, Serialized) { } } - Case (Package () { 2, 6, 10 }) { + Case (Package () { 2, 6, 10, 14 }) { If (PICM) { Return (IQBA) } Else { @@ -85,7 +85,7 @@ Method (IRQM, 1, Serialized) { } } - Case (Package () { 3, 7, 11 }) { + Case (Package () { 3, 7, 11, 15 }) { If (PICM) { Return (IQCA) } Else { @@ -93,7 +93,7 @@ Method (IRQM, 1, Serialized) { } } - Case (Package () { 4, 8, 12 }) { + Case (Package () { 4, 8, 12, 16 }) { If (PICM) { Return (IQDA) } Else { @@ -314,3 +314,71 @@ Device (RP12) Return (IRQM (RPPN)) } } + +Device (RP13) +{ + Name (_ADR, 0x001D0004) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP14) +{ + Name (_ADR, 0x001D0005) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP15) +{ + Name (_ADR, 0x001D0006) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP16) +{ + Name (_ADR, 0x001D0007) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} |