diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-02-10 16:53:53 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-11 16:18:01 +0000 |
| commit | bb4bee8572b6036540e748718851945aa9d36d85 (patch) | |
| tree | 93756f483b55d17ac386bdbab6964b7ddfdfcfeb /src/soc | |
| parent | 2e97897ea39090493e97c576717b83b6cd41b41c (diff) | |
soc/amd/cezanne: select soc-specific ACPI functionality
This doesn't select HAVE_ACPI_TABLES, so no ACPI tables will be
generated for now. There's also no globalnvs.asl that corresponds to
nvs.h yet. The added nvs.h has some currently unused fields, but still
having them in the struct aligns it with Picasso and also might reduce
the noise in future ACPI patches a bit. When most of the ACPI code for
Cezanne has landed, we need to do a cleanup though.
Change-Id: I3d658d284fa67e4da43a89d74686445fd5e93b1f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/cezanne/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/nvs.h | 27 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/southbridge.h | 4 |
3 files changed, 33 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 2de60d7cd0..cfdf6ff354 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -13,6 +13,7 @@ config SOC_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select ACPI_AMD_HARDWARE_SLEEP_VALUES select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select FSP_COMPRESS_FSP_M_LZMA select FSP_COMPRESS_FSP_S_LZMA @@ -23,6 +24,7 @@ config SOC_SPECIFIC_OPTIONS select PLATFORM_USES_FSP2_0 select RESET_VECTOR_IN_RAM select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK_ACPI select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_AOAC select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS diff --git a/src/soc/amd/cezanne/include/soc/nvs.h b/src/soc/amd/cezanne/include/soc/nvs.h new file mode 100644 index 0000000000..7eb6cf6685 --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/nvs.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * NOTE: The layout of the global_nvs structure below must match the layout + * in soc/soc/amd/cezanne/acpi/globalnvs.asl !!! + * + */ + +#ifndef AMD_CEZANNE_NVS_H +#define AMD_CEZANNE_NVS_H + +#include <stdint.h> + +struct __packed global_nvs { + /* Miscellaneous */ + uint8_t unused_was_pcnt; /* 0x00 - Processor Count */ + uint8_t lids; /* 0x01 - LID State */ + uint8_t pwrs; /* 0x02 - AC Power State */ + uint32_t cbmc; /* 0x03 - 0x06 - coreboot Memory Console */ + uint64_t pm1i; /* 0x07 - 0x0e - System Wake Source - PM1 Index */ + uint64_t gpei; /* 0x0f - 0x16 - GPE Wake Source */ + uint8_t tmps; /* 0x17 - Temperature Sensor ID */ + uint8_t tcrt; /* 0x18 - Critical Threshold */ + uint8_t tpsv; /* 0x19 - Passive Threshold */ +}; + +#endif /* AMD_CEZANNE_NVS_H */ diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index dcb5ef1872..0b5882eb6c 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -59,6 +59,10 @@ #define PM_LPC_A20_EN BIT(1) #define PM_LPC_ENABLE BIT(0) +#define PM1_LIMIT 16 +#define GPE0_LIMIT 32 +#define TOTAL_BITS(a) (8 * sizeof(a)) + #define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */ /* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */ |