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authorAamir Bohra <aamir.bohra@intel.com>2020-03-25 15:31:12 +0530
committerFurquan Shaikh <furquan@google.com>2020-04-01 16:39:28 +0000
commita23e0c9d74b7f06738ebf28b068e1bd63f246982 (patch)
tree5afd6c3027ebca12e4d6f94b443fe42dd1f3b75e /src/soc
parent51ce41c0e661fd9cb9207463bcbd920e55b44a62 (diff)
soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC
Switch to using Jasper Lake SoC code from soc/intel/jasperlake and stop referring from soc/intel/tigerlake. Addtionally mainboard changes are done to support build. BUG=b:150217037 TEST=Build and boot waddledoo. Build jasperlake_rvp and volteer board. Change-Id: I39f117bd66cb610a305bcdb8ea65332fd0ff4814 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/jasperlake/Kconfig6
-rw-r--r--src/soc/intel/jasperlake/Makefile.inc2
-rw-r--r--src/soc/intel/jasperlake/romstage/fsp_params.c2
-rw-r--r--src/soc/intel/tigerlake/Kconfig16
-rw-r--r--src/soc/intel/tigerlake/Makefile.inc2
5 files changed, 8 insertions, 20 deletions
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index 01d7294743..844a954996 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -1,9 +1,9 @@
-config SOC_INTEL_JASPERLAKE_COPY
+config SOC_INTEL_JASPERLAKE
bool
help
Intel Jasperlake support
-if SOC_INTEL_JASPERLAKE_COPY
+if SOC_INTEL_JASPERLAKE
config CPU_SPECIFIC_OPTIONS
def_bool y
@@ -192,7 +192,7 @@ config FSP_FD_PATH
depends on FSP_USE_REPO
default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd"
-config SOC_INTEL_JASPERLAKE_COPY_DEBUG_CONSENT
+config SOC_INTEL_JASPERLAKE_DEBUG_CONSENT
int "Debug Consent for JSL"
# USB DBC is more common for developers so make this default to 3 if
# SOC_INTEL_DEBUG_CONSENT=y
diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc
index 29db4f3d00..4a65adc111 100644
--- a/src/soc/intel/jasperlake/Makefile.inc
+++ b/src/soc/intel/jasperlake/Makefile.inc
@@ -1,4 +1,4 @@
-ifeq ($(CONFIG_SOC_INTEL_JASPERLAKE_COPY),y)
+ifeq ($(CONFIG_SOC_INTEL_JASPERLAKE),y)
subdirs-y += romstage
subdirs-y += ../../../cpu/intel/microcode
diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c
index ca7ff26a0e..d263834576 100644
--- a/src/soc/intel/jasperlake/romstage/fsp_params.c
+++ b/src/soc/intel/jasperlake/romstage/fsp_params.c
@@ -89,7 +89,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->SmbusEnable = config->SmbusEnable;
/* Set debug probe type */
- m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_JASPERLAKE_COPY_DEBUG_CONSENT;
+ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_JASPERLAKE_DEBUG_CONSENT;
/* VT-d config */
m_cfg->VtdDisable = 0;
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 63bd881b71..e71586d64b 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -1,22 +1,9 @@
-config SOC_INTEL_TIGERLAKE_BASE
- bool
-
config SOC_INTEL_TIGERLAKE
bool
- select SOC_INTEL_TIGERLAKE_BASE
- #TODO - Enable INTEL_CAR_NEM_ENHANCED
- select INTEL_CAR_NEM
help
Intel Tigerlake support
-config SOC_INTEL_JASPERLAKE
- bool
- select SOC_INTEL_TIGERLAKE_BASE
- select INTEL_CAR_NEM
- help
- Intel Jasperlake support
-
-if SOC_INTEL_TIGERLAKE_BASE
+if SOC_INTEL_TIGERLAKE
config CPU_SPECIFIC_OPTIONS
def_bool y
@@ -36,6 +23,7 @@ config CPU_SPECIFIC_OPTIONS
select INTEL_DESCRIPTOR_MODE_CAPABLE
select HAVE_SMI_HANDLER
select IDT_IN_EVERY_STAGE
+ select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED
select INTEL_GMA_ACPI
select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
select IOAPIC
diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc
index e7169cff42..12d59b1f93 100644
--- a/src/soc/intel/tigerlake/Makefile.inc
+++ b/src/soc/intel/tigerlake/Makefile.inc
@@ -1,4 +1,4 @@
-ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE_BASE),y)
+ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE),y)
subdirs-y += romstage
subdirs-y += ../../../cpu/intel/microcode