soc/amd/cezanne/acpi: Add MMIO devices

The devices were copied from picasso with the following modifications:
* UART{2,3} were deleted
* I2C{0,1} were added
* eMMC was removed since it hasn't been validated

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iddfb975e9292785d0951dd7bb31c1997d2185abd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

4 files changed, 365 insertions, 0 deletions

diff --git a/src/soc/amd/cezanne/acpi/mmio.asl b/src/soc/amd/cezanne/acpi/mmio.asl
new file mode 100644
index 0000000000..3f699dd771
--- /dev/null
+++ b/src/soc/amd/cezanne/acpi/mmio.asl
@@ -0,0 +1,287 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/amd/common/acpi/aoac.asl>
+#include <soc/gpio.h>
+#include <soc/iomap.h>
+#include <amdblocks/acpimmio_map.h>
+
+Device (AAHB)
+{
+	Name (_HID, "AAHB0000")
+	Name (_UID, 0x0)
+	Name (_CRS, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x2000)
+	})
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}
+
+Device (GPIO)
+{
+	Name (_HID, GPIO_DEVICE_NAME)
+	Name (_CID, GPIO_DEVICE_NAME)
+	Name (_UID, 0)
+	Name (_DDN, GPIO_DEVICE_DESC)
+
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Level,
+				ActiveLow,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = IGPI
+		} Else {
+			IRQN = PGPI
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}
+
+Device (FUR0)
+{
+	Name (_HID, "AMDI0020")
+	Name (_UID, 0x0)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = IUA0
+		} Else {
+			IRQN = PUA0
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	AOAC_DEVICE(11, 0)
+}
+
+Device (FUR1) {
+	Name (_HID, "AMDI0020")
+	Name (_UID, 0x1)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = IUA1
+		} Else {
+			IRQN = PUA1
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	AOAC_DEVICE(12, 0)
+}
+
+Device (I2C0) {
+	Name (_HID, "AMDI0010")
+	Name (_UID, 0x0)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I2C0_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II20
+		} Else {
+			IRQN = PI20
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I2C0_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+
+	AOAC_DEVICE(5, 0)
+}
+
+Device (I2C1) {
+	Name (_HID, "AMDI0010")
+	Name (_UID, 0x1)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I2C1_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II21
+		} Else {
+			IRQN = PI21
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I2C1_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+
+	AOAC_DEVICE(6, 0)
+}
+
+Device (I2C2) {
+	Name (_HID, "AMDI0010")
+	Name (_UID, 0x2)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II22
+		} Else {
+			IRQN = PI22
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+
+	AOAC_DEVICE(7, 0)
+}
+
+Device (I2C3)
+{
+	Name (_HID, "AMDI0010")
+	Name (_UID, 0x3)
+	Method (_CRS, 0) {
+		Local0 = ResourceTemplate() {
+			Interrupt (
+				ResourceConsumer,
+				Edge,
+				ActiveHigh,
+				Exclusive, , , IRQR)
+			{ 0 }
+			Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000)
+		}
+		CreateDWordField (Local0, IRQR._INT, IRQN)
+		If (PICM) {
+			IRQN = II23
+		} Else {
+			IRQN = PI23
+		}
+		If (IRQN == 0x1f) {
+			Return (ResourceTemplate() {
+				Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000)
+			})
+		} Else {
+			Return (Local0)
+		}
+	}
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+
+	AOAC_DEVICE(8, 0)
+}
+
+Device (MISC)
+{
+	Name (_HID, "AMD0040")
+	Name (_UID, 0x3)
+	Name (_CRS, ResourceTemplate() {
+		Memory32Fixed (ReadWrite, ACPIMMIO_MISC_BASE, 0x100)
+	})
+	Name (_DSD, Package ()
+	{
+		ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+		Package ()
+		{
+			Package () { "is-rv", 1 },
+		},
+	})
+	Method (_STA, 0x0, NotSerialized)
+	{
+		Return (0x0F)
+	}
+}
diff --git a/src/soc/amd/cezanne/acpi/pci_int_defs.asl b/src/soc/amd/cezanne/acpi/pci_int_defs.asl
new file mode 100644
index 0000000000..4dbaff8a28
--- /dev/null
+++ b/src/soc/amd/cezanne/acpi/pci_int_defs.asl
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* PCI IRQ mapping registers, C00h-C01h. */
+OperationRegion(PRQM, SystemIO, 0x00000c00, 0x00000002)
+	Field(PRQM, ByteAcc, NoLock, Preserve) {
+	PRQI, 0x00000008,
+	PRQD, 0x00000008,  /* Offset: 1h */
+}
+/*
+ * All PIC indexes are prefixed with P.
+ * All IO-APIC indexes are prefixed with I.
+ */
+IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
+	PIRA, 0x00000008,	/* Index 0: INTA */
+	PIRB, 0x00000008,	/* Index 1: INTB */
+	PIRC, 0x00000008,	/* Index 2: INTC */
+	PIRD, 0x00000008,	/* Index 3: INTD */
+	PIRE, 0x00000008,	/* Index 4: INTE */
+	PIRF, 0x00000008,	/* Index 5: INTF */
+	PIRG, 0x00000008,	/* Index 6: INTG */
+	PIRH, 0x00000008,	/* Index 7: INTH */
+
+	Offset (0x43),
+	PMMC, 0x00000008,	/* Index 0x43: eMMC */
+
+	Offset (0x62),
+	PGPI, 0x00000008,	/* Index 0x62: GPIO */
+
+	Offset (0x70),
+	PI20, 0x00000008,	/* Index 0x70: I2C0 */
+	PI21, 0x00000008,	/* Index 0x71: I2C1 */
+	PI22, 0x00000008,	/* Index 0x72: I2C2 */
+	PI23, 0x00000008,	/* Index 0x73: I2C3 */
+	PUA0, 0x00000008,	/* Index 0x74: UART0 */
+	PUA1, 0x00000008,	/* Index 0x75: UART1 */
+	PI24, 0x00000008,	/* Index 0x76: I2C4 */
+	PI25, 0x00000008,	/* Index 0x77: I2C5 */
+
+	/* IO-APIC IRQs */
+	Offset (0x80),
+	IORA, 0x00000008,	/* Index 0x80: INTA */
+	IORB, 0x00000008,	/* Index 0x81: INTB */
+	IORC, 0x00000008,	/* Index 0x82: INTC */
+	IORD, 0x00000008,	/* Index 0x83: INTD */
+	IORE, 0x00000008,	/* Index 0x84: INTE */
+	IORF, 0x00000008,	/* Index 0x85: INTF */
+	IORG, 0x00000008,	/* Index 0x86: INTG */
+	IORH, 0x00000008,	/* Index 0x87: INTH */
+
+	Offset (0xC3),
+	IMMC, 0x00000008,	/* Index 0xC3: eMMC */
+
+	Offset (0xE2),
+	IGPI, 0x00000008,	/* Index 0xE2: GPIO */
+
+	Offset (0xF0),
+	II20, 0x00000008,	/* Index 0xF0: I2C0 */
+	II21, 0x00000008,	/* Index 0xF1: I2C1 */
+	II22, 0x00000008,	/* Index 0xF2: I2C2 */
+	II23, 0x00000008,	/* Index 0xF3: I2C3 */
+	IUA0, 0x00000008,	/* Index 0xF4: UART0 */
+	IUA1, 0x00000008,	/* Index 0xF5: UART1 */
+	II24, 0x00000008,	/* Index 0xF6: I2C4 */
+	II25, 0x00000008,	/* Index 0xF7: I2C5 */
+}
diff --git a/src/soc/amd/cezanne/acpi/soc.asl b/src/soc/amd/cezanne/acpi/soc.asl
index e472ec680a..618aa11297 100644
--- a/src/soc/amd/cezanne/acpi/soc.asl
+++ b/src/soc/amd/cezanne/acpi/soc.asl
@@ -5,4 +5,8 @@ Scope(\_SB) {
 	#include <arch/x86/acpi/globutil.asl>
 
 	#include <soc/amd/common/acpi/gpio_bank_lib.asl>
+
+	#include "pci_int_defs.asl"
+
+	#include "mmio.asl"
 } /* End \_SB scope */
diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h
index 0d59c2c47c..3a84fae4c7 100644
--- a/src/soc/amd/cezanne/include/soc/iomap.h
+++ b/src/soc/amd/cezanne/include/soc/iomap.h
@@ -3,6 +3,8 @@
 #ifndef AMD_CEZANNE_IOMAP_H
 #define AMD_CEZANNE_IOMAP_H
 
+#if ENV_X86
+
 /* MMIO Ranges */
 #define SPI_BASE_ADDRESS		0xfec10000
 
@@ -14,6 +16,11 @@
 /* FCH AL2AHB Registers */
 #define ALINK_AHB_ADDRESS		0xfedc0000
 
+#define APU_I2C0_BASE			0xfedc2000
+#define APU_I2C1_BASE			0xfedc3000
+#define APU_I2C2_BASE			0xfedc4000
+#define APU_I2C3_BASE			0xfedc5000
+
 #define APU_DMAC0_BASE			0xfedc7000
 #define APU_DMAC1_BASE			0xfedc8000
 #define APU_UART0_BASE			0xfedc9000
@@ -21,6 +28,8 @@
 
 #define FLASH_BASE_ADDR			((0xffffffff - CONFIG_ROM_SIZE) + 1)
 
+#endif /* ENV_X86 */
+
 /* I/O Ranges */
 #define NCP_ERR				0x00f0
 #define ACPI_IO_BASE		0x0400