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authorSubrata Banik <subrata.banik@intel.com>2020-08-30 13:51:44 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-09-01 03:06:04 +0000
commit8e6d5f2937c169914e46b5ebc973e5df5e4290a7 (patch)
tree1550c8877877a7a9b197da65bcff76f878bee560 /src/soc
parentb7a68d5b05259a07a84a546e6a7e40948ba705ac (diff)
{include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistent
Convert 0X -> 0x Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Iea3ca67908135d0e85083a05bad2ea176ca34095 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/quark/include/soc/cpu.h2
-rw-r--r--src/soc/intel/quark/include/soc/pci_devs.h2
-rw-r--r--src/soc/mediatek/mt8183/gpio.c2
-rw-r--r--src/soc/mediatek/mt8183/include/soc/pmic_wrap.h10
-rw-r--r--src/soc/nvidia/tegra124/include/soc/sdram_param.h2
-rw-r--r--src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c14
-rw-r--r--src/soc/nvidia/tegra210/include/soc/sdram_param.h2
-rw-r--r--src/soc/rockchip/rk3399/clock.c2
8 files changed, 18 insertions, 18 deletions
diff --git a/src/soc/intel/quark/include/soc/cpu.h b/src/soc/intel/quark/include/soc/cpu.h
index 84bce7dc51..e4bcab1b93 100644
--- a/src/soc/intel/quark/include/soc/cpu.h
+++ b/src/soc/intel/quark/include/soc/cpu.h
@@ -6,6 +6,6 @@
#include <device/device.h>
/* Supported CPUIDs */
-#define CPUID_QUARK_X1000 0X590
+#define CPUID_QUARK_X1000 0x590
#endif /* _QUARK_CPU_H_ */
diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h
index 95e5f28507..2c6a53229b 100644
--- a/src/soc/intel/quark/include/soc/pci_devs.h
+++ b/src/soc/intel/quark/include/soc/pci_devs.h
@@ -13,7 +13,7 @@
#define I2CGPIO_DEVID 0x0934
#define HSUART_DEVID 0x0936
#define EHCI_DEVID 0x0939
-#define LPC_DEVID 0X095E
+#define LPC_DEVID 0x095E
#define PCIE_PORT0_DEVID 0x11c3
#define PCIE_PORT1_DEVID 0x11c4
diff --git a/src/soc/mediatek/mt8183/gpio.c b/src/soc/mediatek/mt8183/gpio.c
index 6565ec5bd8..0c0b54d73a 100644
--- a/src/soc/mediatek/mt8183/gpio.c
+++ b/src/soc/mediatek/mt8183/gpio.c
@@ -10,7 +10,7 @@ enum {
SEL_OFFSET = 0x80,
EH_RSEL_OFFSET = 0xF0,
GPIO_DRV0_OFFSET = 0xA0,
- GPIO_DRV1_OFFSET = 0XB0,
+ GPIO_DRV1_OFFSET = 0xB0,
};
static void gpio_set_pull_pupd(gpio_t gpio, enum pull_enable enable,
diff --git a/src/soc/mediatek/mt8183/include/soc/pmic_wrap.h b/src/soc/mediatek/mt8183/include/soc/pmic_wrap.h
index 2c1fa9b948..8cfe8b0aa3 100644
--- a/src/soc/mediatek/mt8183/include/soc/pmic_wrap.h
+++ b/src/soc/mediatek/mt8183/include/soc/pmic_wrap.h
@@ -351,22 +351,22 @@ enum {
};
enum {
- STA_PD_98_5_US = 0X5,
+ STA_PD_98_5_US = 0x5,
};
enum {
- WATCHDOG_TIMER_7_5_MS = 0XF,
+ WATCHDOG_TIMER_7_5_MS = 0xF,
};
enum {
- WDT_MONITOR_ALL = 0XFFFF,
+ WDT_MONITOR_ALL = 0xFFFF,
};
enum {
MONITOR_LATCH_MATCHED_TRANS = 0x1 << 28,
STARV_15 = 0x1 << 24,
DCXO = 0x1 << 19,
- MONITOR_ALL_INT = 0XFFFFFFFF,
+ MONITOR_ALL_INT = 0xFFFFFFFF,
INT0_MONITOR = MONITOR_ALL_INT,
INT1_MONITOR = MONITOR_ALL_INT &
~MONITOR_LATCH_MATCHED_TRANS & ~STARV_15 & ~DCXO,
@@ -396,6 +396,6 @@ enum {
};
enum {
- DUMMY_READ_CYCLES = 0X8,
+ DUMMY_READ_CYCLES = 0x8,
};
#endif /* __SOC_MEDIATEK_MT8183_PMIC_WRAP_H__ */
diff --git a/src/soc/nvidia/tegra124/include/soc/sdram_param.h b/src/soc/nvidia/tegra124/include/soc/sdram_param.h
index 45cd9143c7..b19ae5fa7f 100644
--- a/src/soc/nvidia/tegra124/include/soc/sdram_param.h
+++ b/src/soc/nvidia/tegra124/include/soc/sdram_param.h
@@ -35,7 +35,7 @@ enum {
NvBootMemoryType_Num,
/* Specifies an entry in the ram_code table that's not in use */
- NvBootMemoryType_Unused = 0X7FFFFFF,
+ NvBootMemoryType_Unused = 0x7FFFFFF,
};
enum {
diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
index 85d331b5ce..b7881de6a1 100644
--- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
+++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
@@ -2,14 +2,14 @@
/* Function unit addresses. */
enum {
- UP_TAG_BASE = 0X60000000,
- TIMER_BASE = 0X60005000,
- CLK_RST_BASE = 0X60006000,
- FLOW_CTLR_BASE = 0X60007000,
+ UP_TAG_BASE = 0x60000000,
+ TIMER_BASE = 0x60005000,
+ CLK_RST_BASE = 0x60006000,
+ FLOW_CTLR_BASE = 0x60007000,
TEGRA_EVP_BASE = 0x6000f000,
- PMC_CTLR_BASE = 0X7000e400,
- MC_CTLR_BASE = 0X70019000,
- SYSCTR_CTLR_BASE = 0X700f0000
+ PMC_CTLR_BASE = 0x7000e400,
+ MC_CTLR_BASE = 0x70019000,
+ SYSCTR_CTLR_BASE = 0x700f0000
};
diff --git a/src/soc/nvidia/tegra210/include/soc/sdram_param.h b/src/soc/nvidia/tegra210/include/soc/sdram_param.h
index 7513302d05..f9d7c6b592 100644
--- a/src/soc/nvidia/tegra210/include/soc/sdram_param.h
+++ b/src/soc/nvidia/tegra210/include/soc/sdram_param.h
@@ -38,7 +38,7 @@ enum {
NvBootMemoryType_Num,
/* Specifies an entry in the ram_code table that's not in use */
- NvBootMemoryType_Unused = 0X7FFFFFF,
+ NvBootMemoryType_Unused = 0x7FFFFFF,
};
enum {
diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c
index ea1d7ff531..0ba07d6137 100644
--- a/src/soc/rockchip/rk3399/clock.c
+++ b/src/soc/rockchip/rk3399/clock.c
@@ -81,7 +81,7 @@ enum {
PLL_SSMOD_RESET_SHIFT = 2,
PLL_SSMOD_DOWNSPEAD_MASK = 1,
PLL_SSMOD_DOWNSPEAD_SHIFT = 3,
- PLL_SSMOD_DIVVAL_MASK = 0Xf,
+ PLL_SSMOD_DIVVAL_MASK = 0xf,
PLL_SSMOD_DIVVAL_SHIFT = 4,
PLL_SSMOD_SPREADAMP_MASK = 0x1f,
PLL_SSMOD_SPREADAMP_SHIFT = 8,