memlayout: Store region sizes as separate symbols

This patch changes the memlayout macro infrastructure so that the size
of a region "xxx" (i.e. the distance between the symbols _xxx and _exxx)
is stored in a separate _xxx_size symbol. This has the advantage that
region sizes can be used inside static initializers, and also saves an
extra subtraction at runtime. Since linker symbols can only be treated
as addresses (not as raw integers) by C, retain the REGION_SIZE()
accessor macro to hide the necessary typecast.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ifd89708ca9bd3937d0db7308959231106a6aa373
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

10 files changed, 26 insertions, 29 deletions

diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
index ff6aebf3fb..e5044e6d43 100644
--- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
+++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
@@ -4,11 +4,11 @@
 #include <arch/header.ld>
 #include <soc/psp_transfer.h>
 
-#define EARLY_RESERVED_DRAM_START(addr)		SYMBOL(early_reserved_dram, addr)
-#define EARLY_RESERVED_DRAM_END(addr)		SYMBOL(eearly_reserved_dram, addr)
+#define EARLY_RESERVED_DRAM_START(addr)		REGION_START(early_reserved_dram, addr)
+#define EARLY_RESERVED_DRAM_END(addr)		REGION_END(early_reserved_dram, addr)
 
-#define PSP_SHAREDMEM_DRAM_START(addr)		SYMBOL(psp_sharedmem_dram, addr)
-#define PSP_SHAREDMEM_DRAM_END(addr)		SYMBOL(epsp_sharedmem_dram, addr)
+#define PSP_SHAREDMEM_DRAM_START(addr)		REGION_START(psp_sharedmem_dram, addr)
+#define PSP_SHAREDMEM_DRAM_END(addr)		REGION_END(psp_sharedmem_dram, addr)
 
 BOOTBLOCK_END = CONFIG_ROMSTAGE_ADDR;
 BOOTBLOCK_ADDR = BOOTBLOCK_END - CONFIG_C_ENV_BOOTBLOCK_SIZE;
diff --git a/src/soc/mediatek/mt8173/memlayout.ld b/src/soc/mediatek/mt8173/memlayout.ld
index d9a6d8312d..092cfdf2bf 100644
--- a/src/soc/mediatek/mt8173/memlayout.ld
+++ b/src/soc/mediatek/mt8173/memlayout.ld
@@ -9,8 +9,8 @@
  * It will be returned before starting the ramstage.
  * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able.
  */
-#define SRAM_L2C_START(addr) SYMBOL(sram_l2c, addr)
-#define SRAM_L2C_END(addr) SYMBOL(esram_l2c, addr)
+#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr)
+#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr)
 
 #define DRAM_DMA(addr, size) \
 	REGION(dram_dma, addr, size, 4K) \
diff --git a/src/soc/mediatek/mt8183/memlayout.ld b/src/soc/mediatek/mt8183/memlayout.ld
index a549274376..0acd174c84 100644
--- a/src/soc/mediatek/mt8183/memlayout.ld
+++ b/src/soc/mediatek/mt8183/memlayout.ld
@@ -9,8 +9,8 @@
  * It will be returned before starting the ramstage.
  * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able.
  */
-#define SRAM_L2C_START(addr) SYMBOL(sram_l2c, addr)
-#define SRAM_L2C_END(addr) SYMBOL(esram_l2c, addr)
+#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr)
+#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr)
 #define DRAM_INIT_CODE(addr, size) \
 	REGION(dram_init_code, addr, size, 4)
 
diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld
index 6f964f2331..2624d82c55 100644
--- a/src/soc/mediatek/mt8192/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld
@@ -9,8 +9,8 @@
  * It will be returned before starting the ramstage.
  * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able.
  */
-#define SRAM_L2C_START(addr) SYMBOL(sram_l2c, addr)
-#define SRAM_L2C_END(addr) SYMBOL(esram_l2c, addr)
+#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr)
+#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr)
 #define DRAM_INIT_CODE(addr, size) \
 	REGION(dram_init_code, addr, size, 64K)
 
diff --git a/src/soc/qualcomm/ipq40xx/memlayout.ld b/src/soc/qualcomm/ipq40xx/memlayout.ld
index 4c542949cd..e630e74ebd 100644
--- a/src/soc/qualcomm/ipq40xx/memlayout.ld
+++ b/src/soc/qualcomm/ipq40xx/memlayout.ld
@@ -4,9 +4,6 @@
 
 #include <arch/header.ld>
 
-#define REGION_START(name, addr)	SYMBOL(name, addr)
-#define REGION_END(name, addr)		SYMBOL(e##name, addr)
-
 SECTIONS
 {
 	REGION(oc_imem, 0x08600000, 32K, 0)
diff --git a/src/soc/qualcomm/qcs405/memlayout.ld b/src/soc/qualcomm/qcs405/memlayout.ld
index a2825121b1..348fb43cf5 100644
--- a/src/soc/qualcomm/qcs405/memlayout.ld
+++ b/src/soc/qualcomm/qcs405/memlayout.ld
@@ -4,12 +4,12 @@
 #include <arch/header.ld>
 
 /* SYSTEM_IMEM : 0x8600000 - 0x8607FFF */
-#define SSRAM_START(addr) SYMBOL(ssram, addr)
-#define SSRAM_END(addr) SYMBOL(essram, addr)
+#define SSRAM_START(addr) REGION_START(ssram, addr)
+#define SSRAM_END(addr) REGION_END(ssram, addr)
 
 /* BOOT_IMEM   : 0x8C00000 - 0x8D80000 */
-#define BSRAM_START(addr) SYMBOL(bsram, addr)
-#define BSRAM_END(addr) SYMBOL(ebsram, addr)
+#define BSRAM_START(addr) REGION_START(bsram, addr)
+#define BSRAM_END(addr) REGION_END(bsram, addr)
 
 SECTIONS
 {
diff --git a/src/soc/qualcomm/sc7180/memlayout.ld b/src/soc/qualcomm/sc7180/memlayout.ld
index ca9c993920..1b9044f691 100644
--- a/src/soc/qualcomm/sc7180/memlayout.ld
+++ b/src/soc/qualcomm/sc7180/memlayout.ld
@@ -4,16 +4,16 @@
 #include <arch/header.ld>
 
 /* SYSTEM_IMEM : 0x14680000 - 0x146AE000 */
-#define SSRAM_START(addr) SYMBOL(ssram, addr)
-#define SSRAM_END(addr) SYMBOL(essram, addr)
+#define SSRAM_START(addr) REGION_START(ssram, addr)
+#define SSRAM_END(addr) REGION_END(ssram, addr)
 
 /* BOOT_IMEM   : 0x14800000 - 0x14980000 */
-#define BSRAM_START(addr) SYMBOL(bsram, addr)
-#define BSRAM_END(addr) SYMBOL(ebsram, addr)
+#define BSRAM_START(addr) REGION_START(bsram, addr)
+#define BSRAM_END(addr) REGION_END(bsram, addr)
 
 /* AOP : 0x0B000000 - 0x0B100000 */
-#define AOPSRAM_START(addr) SYMBOL(aopsram, addr)
-#define AOPSRAM_END(addr) SYMBOL(eaopsram, addr)
+#define AOPSRAM_START(addr) REGION_START(aopsram, addr)
+#define AOPSRAM_END(addr) REGION_END(aopsram, addr)
 
 SECTIONS
 {
diff --git a/src/soc/rockchip/rk3288/memlayout.ld b/src/soc/rockchip/rk3288/memlayout.ld
index 4ef0163def..32962257b2 100644
--- a/src/soc/rockchip/rk3288/memlayout.ld
+++ b/src/soc/rockchip/rk3288/memlayout.ld
@@ -28,8 +28,8 @@ SECTIONS
 
 	/* 4K of special SRAM in PMU power domain.
 	 * Careful: only supports 32-bit wide write accesses! */
-	SYMBOL(pmu_sram, 0xFF720000)
+	REGION_START(pmu_sram, 0xFF720000)
 	TTB_SUBTABLES(0xFF720800, 1K)
 	WATCHDOG_TOMBSTONE(0xFF720FFC, 4)
-	SYMBOL(epmu_sram, 0xFF721000)
+	REGION_END(pmu_sram, 0xFF721000)
 }
diff --git a/src/soc/rockchip/rk3399/memlayout.ld b/src/soc/rockchip/rk3399/memlayout.ld
index aa925a25c9..7a4fb70cfc 100644
--- a/src/soc/rockchip/rk3399/memlayout.ld
+++ b/src/soc/rockchip/rk3399/memlayout.ld
@@ -12,9 +12,9 @@ SECTIONS
 	DMA_COHERENT(0x10000000, 2M)
 
 	/* 8K of special SRAM in PMU power domain. */
-	SYMBOL(pmu_sram, 0xFF3B0000)
+	REGION_START(pmu_sram, 0xFF3B0000)
 	WATCHDOG_TOMBSTONE(0xFF3B1FFC, 4)
-	SYMBOL(epmu_sram, 0xFF3B2000)
+	REGION_END(pmu_sram, 0xFF3B2000)
 
 	SRAM_START(0xFF8C0000)
 #if ENV_RAMSTAGE
diff --git a/src/soc/sifive/fu540/memlayout.ld b/src/soc/sifive/fu540/memlayout.ld
index b365b96563..73faa4b4e8 100644
--- a/src/soc/sifive/fu540/memlayout.ld
+++ b/src/soc/sifive/fu540/memlayout.ld
@@ -5,8 +5,8 @@
 
 #include <arch/header.ld>
 
-#define L2LIM_START(addr) SYMBOL(l2lim, addr)
-#define L2LIM_END(addr) SYMBOL(el2lim, addr)
+#define L2LIM_START(addr) REGION_START(l2lim, addr)
+#define L2LIM_END(addr) REGION_END(l2lim, addr)
 
 SECTIONS
 {