diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-06-04 16:09:44 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-06-09 17:02:26 +0200 |
| commit | 72179fad42e2858b08719061cccb2768f4546d17 (patch) | |
| tree | ed5b6d29d97f9a96fbe7f241169999274fa762d6 /src/soc | |
| parent | 96fbc31027b8e208c264d96c04f45799cea3417e (diff) | |
soc/intel/quark: Pass serial port address to FSP
Pass the serial port address to FSP using a UPD value in the MemoryInit
API.
TEST=Build and run on Galileo Gen2
Change-Id: I86449d80310b7b34ac503ebd2671a4052b080730
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15079
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/quark/romstage/romstage.c | 23 |
1 files changed, 18 insertions, 5 deletions
diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index e27aa685be..62f8b212e5 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -132,6 +132,24 @@ void soc_memory_init_params(struct romstage_params *params, printk(BIOS_SPEW, "Clearing SMI interrupts and wake events\n"); reg_script_run_on_dev(LPC_BDF, clear_smi_and_wake_events); } + + /* Update the UPD data for MemoryInit */ + printk(BIOS_DEBUG, "Updating UPD values for MemoryInit: 0x%p\n", upd); + upd->PcdSerialRegisterBase = UART_BASE_ADDRESS; + upd->PcdSmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? + config->PcdSmmTsegSize : 0; +} + +void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, + MEMORY_INIT_UPD *new) +{ + /* Display the parameters for MemoryInit */ + printk(BIOS_SPEW, "UPD values for MemoryInit at: 0x%p\n", new); + fsp_display_upd_value("PcdSerialRegisterBase", + sizeof(old->PcdSerialRegisterBase), + old->PcdSerialRegisterBase, new->PcdSerialRegisterBase); + fsp_display_upd_value("PcdSmmTsegSize", sizeof(old->PcdSmmTsegSize), + old->PcdSmmTsegSize, new->PcdSmmTsegSize); } void soc_after_ram_init(struct romstage_params *params) @@ -157,8 +175,3 @@ void soc_after_ram_init(struct romstage_params *params) /* Initialize the PCIe bridges */ pcie_init(); } - -void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, - MEMORY_INIT_UPD *new) -{ -} |