diff options
| author | Martin Roth <martin@coreboot.org> | 2020-07-15 10:05:33 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2020-07-16 17:38:57 +0000 |
| commit | 6812626382548691e1b7c4828175859ee3fd0144 (patch) | |
| tree | 9304f8d76f223833dea6f98ff0f3445f3b034391 /src/soc | |
| parent | 79ab7d7780bfb0a23748afdd5b4832e23544b4df (diff) | |
soc/amd/stoneyridge: Remove unused SPI #defines
These #defines are not used, and conflict with #defines in
amdblocks/spi.h
BUG=None
TEST=Build stoney platforms
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I29b77a6b21a4deda6f28f5b057988cf3921540e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 601ceaddec..80c258f442 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -255,8 +255,6 @@ #define SPI_FIFO_PTR_CLR BIT(20) #define SPI_ARB_ENABLE BIT(19) #define EXEC_OPCODE BIT(16) -#define SPI_FIFO 0x80 -#define SPI_FIFO_DEPTH (0xc7 - SPI_FIFO) #define SPI100_ENABLE 0x20 #define SPI_USE_SPI100 BIT(0) |