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authorTom Warren <twarren@nvidia.com>2015-05-21 15:21:12 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-06-23 22:58:32 +0200
commit355dc1e66ae4de309ec801a1d168fe98dd4ca3f1 (patch)
tree50d11d67f70a8f1d81e02314f4aef82e6fbcf65a /src/soc
parent018216d120bc19da71e2586a7b437d56ec07494e (diff)
nvidia/tegra: expose more registers
This is in preparation for t210 Change-Id: I3e640b1f7fc583518361527dec4c3c1072c80251 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e762d4bde1a18691257453e4b87a0bb42a0a2d7c Original-Change-Id: Ida096106bb0137c07ad62d2df06628e37f0d884c Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/272754 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10632 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/nvidia/tegra/apbmisc.h12
1 files changed, 10 insertions, 2 deletions
diff --git a/src/soc/nvidia/tegra/apbmisc.h b/src/soc/nvidia/tegra/apbmisc.h
index 835e466978..3a26e4180e 100644
--- a/src/soc/nvidia/tegra/apbmisc.h
+++ b/src/soc/nvidia/tegra/apbmisc.h
@@ -23,9 +23,11 @@
#include <stdint.h>
struct apbmisc {
- u32 reserved0[9]; /* ABP_MISC_PP_ offsets 00-20 */
+ u32 reserved0[2]; /* ABP_MISC_PP_ offsets 00 and 04 */
+ u32 pp_strapping_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
+ u32 reserved1[6]; /* ABP_MISC_PP_ offsets 0C-20 */
u32 pp_config_ctl; /* _CONFIG_CTL_0, offset 24 */
- u32 reserved1[6]; /* APB_MISC_PP_ offsets 28-3C */
+ u32 reserved2[6]; /* APB_MISC_PP_ offsets 28-3C */
u32 pp_pinmux_global; /* _PINMUX_GLOBAL_0, offset 40 */
};
@@ -49,4 +51,10 @@ void enable_jtag(void);
void clamp_tristate_inputs(void);
void tegra_revision_info(struct tegra_revision *id);
+enum {
+ PP_STRAPPING_OPT_A_RAM_CODE_SHIFT = 4,
+ PP_STRAPPING_OPT_A_RAM_CODE_MASK =
+ 0xF << PP_STRAPPING_OPT_A_RAM_CODE_SHIFT,
+};
+
#endif /* __SOC_NVIDIA_TEGRA_APBMISC_H__ */