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authorLijian Zhao <lijian.zhao@intel.com>2018-09-25 15:52:03 -0700
committerPatrick Georgi <pgeorgi@google.com>2018-09-28 09:53:59 +0000
commit1d900935df918318e198ae61eb8bf42ef1edf674 (patch)
treea33dc88a6c4331a85ab830fff18aec4f01217fe9 /src/soc
parent4586ccdfe6e62e6c104f65f798e6242c7a146333 (diff)
soc/intel/cannonlake: Add ACPI entry for LAN
Add ACPI DSDT entry for integrated Gigabit LAN controller. Change-Id: I15bf1d4065894531871380b3318f553b637f4a97 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28743 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/cannonlake/acpi/pch_glan.asl29
-rw-r--r--src/soc/intel/cannonlake/acpi/southbridge.asl5
2 files changed, 33 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/acpi/pch_glan.asl b/src/soc/intel/cannonlake/acpi/pch_glan.asl
new file mode 100644
index 0000000000..260dd44962
--- /dev/null
+++ b/src/soc/intel/cannonlake/acpi/pch_glan.asl
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2017-2108 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Intel Gigabit Ethernet Controller 0:1f.6 */
+
+Device (GLAN)
+{
+ Name (_ADR, 0x001f0006)
+
+ Name (_S0W, 3)
+
+ Name (_PRW, Package() {GPE0_PME_B0, 4})
+
+ Method (_DSW, 3) {}
+}
diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl
index e4f29b6a37..6fac398619 100644
--- a/src/soc/intel/cannonlake/acpi/southbridge.asl
+++ b/src/soc/intel/cannonlake/acpi/southbridge.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2017 Intel Corp.
+ * Copyright (C) 2017-2018 Intel Corp.
* (Written by Bora Guvendik <bora.guvendik@intel.com> for Intel Corp.)
*
* This program is free software; you can redistribute it and/or modify
@@ -48,3 +48,6 @@
/* CNVi */
#include "cnvi.asl"
+
+/* GBe 0:1f.6 */
+#include "pch_glan.asl"