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authorAaron Durbin <adurbin@chromium.org>2015-07-30 13:30:03 -0500
committerPatrick Georgi <pgeorgi@google.com>2015-08-29 07:09:38 +0000
commit1244c2c961de413a8c73914f9801dcec7e31b09d (patch)
tree6d0e9d56aee19b70ff3f36634493009f2c853b40 /src/soc
parent5c9a71e9d5215593a75de907ce085651f1198d97 (diff)
intel/braswell: remove CBFS_SIZE option in SoC directory
CBFS_SIZE is living as a mainboard attribute. Because of the Kconfig include ordering the SoC *cannot* set the default. BUG=chrome-os-partner:43419 BRANCH=None TEST=None Change-Id: If34e8fd965573fdc7f57b63201dbcb5256e132d6 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: a820b11a0aa3b820c79b1f76b15370d969153175 Original-Change-Id: I7ba637e66878f5ae9caedb63fdd37ed7e375224e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289832 Original-Reviewed-by: Martin Roth <martinroth@google.com> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11410 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/braswell/Kconfig12
1 files changed, 0 insertions, 12 deletions
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 4f7ed6a7ca..a3f6025654 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -117,18 +117,6 @@ config RESET_ON_INVALID_RAMSTAGE_CACHE
the system will reset otherwise the ramstage will be reloaded from
cbfs.
-config CBFS_SIZE
- hex "Size of CBFS filesystem in ROM"
- default 0x100000
- help
- The firmware image has to store a lot more than just coreboot,
- including:
- - a firmware descriptor
- - Intel Management Engine firmware
- - MRC cache information
- This option allows to limit the size of the CBFS portion in the
- firmware image.
-
config LOCK_MANAGEMENT_ENGINE
bool "Lock Management Engine section"
default n