diff options
| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2018-12-29 20:29:50 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-01-01 13:31:36 +0000 |
| commit | 09f7382935e03bc83c66878fc6d41bd2b556ccd3 (patch) | |
| tree | 72821d9c7895335b18f990ebe861109c961251ba /src/soc | |
| parent | 126c27da064ec5e8d141a9b637ba8ed9c59a5b29 (diff) | |
soc/intel/cannonlake: Enable CNVi based on devicetree
Set PchCnvimode to Auto if CNVi is enabled in device tree. This will
allow FSP to configure CNVi.
Change-Id: I4f77fe5e9f561d3b498403e42dfc7afdcfaedf6f
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/30516
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/cannonlake/fsp_params.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 78b27e9514..8166dea691 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -162,6 +162,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) dev->enabled = 0; params->XdciEnable = dev->enabled; + /* Enable CNVi Wifi if enabled in device tree */ + dev = dev_find_slot(0, PCH_DEVFN_CNViWIFI); + params->PchCnviMode = dev->enabled; + /* PCI Express */ for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) { if (config->PcieClkSrcUsage[i] == 0) |