summaryrefslogtreecommitdiff
path: root/src/soc
diff options
context:
space:
mode:
authorDuncan Laurie <dlaurie@chromium.org>2013-10-22 16:35:12 -0700
committerIsaac Christensen <isaac.christensen@se-eng.com>2014-09-08 19:05:11 +0200
commitfe74092c4e802efbed76804fb43f0bd25a5721b2 (patch)
treee9d9b5a592f88f495875831111edbb034a46178e /src/soc
parent50fc0b4cabcff9680aa53aaeaf1a54dc8e7d12de (diff)
samus: Fix up memory SPD information
The LPDDR3 memory is x32 and dual rank with 14 row bits. In addition the memory is actually elpida, even though they are owned by micron it is confusing to label it as such. And the ram strap options were inverted from what I expected so the memory table needs to be updated. Change-Id: Ia29a23e8140d884fb84f940806f041b40562aab9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174121 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 0d63d36b8035165f95db798ed40488519e622a65) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6828 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc')
0 files changed, 0 insertions, 0 deletions