diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2016-11-01 21:33:12 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2016-11-03 05:36:03 +0100 |
| commit | d36ed272b2d2d082889a7f21414904badc2c2936 (patch) | |
| tree | d6fc3c7b11b348b02ad91309e41403d767c35a69 /src/soc | |
| parent | 6372a0eef14dd97f2743d7d1820e2446cc997bd2 (diff) | |
soc/intel/apollolake: Implement SPI flash status register read
This was a dummy implementation until now which returned -1 always. Add
support for reading SPI flash status register (srp0).
BUG=chrome-os-partner:59267
BRANCH=None
TEST=Verified by enabling and disabling write-protect on reef that the
value of SRP0 changes accordingly in status register read.
Change-Id: Ib1349605dd87c4a087e416f52a8256b1eaac4f4c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17205
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/apollolake/spi.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/src/soc/intel/apollolake/spi.c b/src/soc/intel/apollolake/spi.c index 85bc0b6a32..8cb8aa5d6d 100644 --- a/src/soc/intel/apollolake/spi.c +++ b/src/soc/intel/apollolake/spi.c @@ -313,8 +313,16 @@ static int nuclear_spi_write(struct spi_flash *flash, static int nuclear_spi_status(struct spi_flash *flash, uint8_t *reg) { - printk(BIOS_DEBUG, "NOT IMPLEMENTED: %s() !!!\n", __func__); - return E_NOT_IMPLEMENTED; + int ret; + BOILERPLATE_CREATE_CTX(ctx); + + ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_RD_STATUS, 0, + sizeof(*reg)); + if (ret != SUCCESS) + return ret; + + drain_xfer_fifo(ctx, reg, sizeof(*reg)); + return ret; } static struct spi_slave boot_spi CAR_GLOBAL; |