arch/mips: Fix <arch/mmio.h> prototypes

These signatures need to be consistent across different
architectures.

Change-Id: Ide8502ee8cda8995828c77fe1674d8ba6f3aa15f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

9 files changed, 227 insertions, 227 deletions

diff --git a/src/soc/imgtec/pistachio/clocks.c b/src/soc/imgtec/pistachio/clocks.c
index 7957086804..aa54ebc43e 100644
--- a/src/soc/imgtec/pistachio/clocks.c
+++ b/src/soc/imgtec/pistachio/clocks.c
@@ -236,56 +236,56 @@ static int pll_setup(struct pll_parameters *param, u8 divider1, u8 divider2)
 		~(param->postdiv2_mask)));
 
 	/* Temporary bypass PLL (select XTAL as clock input) */
-	reg = read32(PISTACHIO_CLOCK_SWITCH);
+	reg = read32_x(PISTACHIO_CLOCK_SWITCH);
 	reg &= ~(param->external_bypass_mask);
-	write32(PISTACHIO_CLOCK_SWITCH, reg);
+	write32_x(PISTACHIO_CLOCK_SWITCH, reg);
 
 	/* Un-bypass PLL's internal bypass */
-	reg = read32(param->ctrl_addr);
+	reg = read32_x(param->ctrl_addr);
 	reg &= ~(param->internal_bypass_mask);
-	write32(param->ctrl_addr, reg);
+	write32_x(param->ctrl_addr, reg);
 
 	/* Disable power down */
-	reg = read32(param->power_down_ctrl_addr);
+	reg = read32_x(param->power_down_ctrl_addr);
 	reg &= ~(param->power_down_ctrl_mask);
-	write32(param->power_down_ctrl_addr, reg);
+	write32_x(param->power_down_ctrl_addr, reg);
 
 	/* Noise cancellation */
 	if (param->dacpd_addr) {
-		reg = read32(param->dacpd_addr);
+		reg = read32_x(param->dacpd_addr);
 		reg &= ~(param->dacpd_mask);
-		write32(param->dacpd_addr, reg);
+		write32_x(param->dacpd_addr, reg);
 	}
 
 	/* Functional mode */
 	if (param->dsmpd_addr) {
-		reg = read32(param->dsmpd_addr);
+		reg = read32_x(param->dsmpd_addr);
 		reg &= ~(param->dsmpd_mask);
-		write32(param->dsmpd_addr, reg);
+		write32_x(param->dsmpd_addr, reg);
 	}
 
 	if (param->feedback_addr) {
 		assert(!((param->feedback << param->feedback_shift) &
 			~(param->feedback_mask)));
-		reg = read32(param->feedback_addr);
+		reg = read32_x(param->feedback_addr);
 		reg &= ~(param->feedback_mask);
 		reg |= (param->feedback << param->feedback_shift) &
 			param->feedback_mask;
-		write32(param->feedback_addr, reg);
+		write32_x(param->feedback_addr, reg);
 	}
 
 	if (param->refdiv_addr) {
 		assert(!((param->refdivider << param->refdiv_shift) &
 			~(param->refdiv_mask)));
-		reg = read32(param->refdiv_addr);
+		reg = read32_x(param->refdiv_addr);
 		reg &= ~(param->refdiv_mask);
 		reg |= (param->refdivider << param->refdiv_shift) &
 			param->refdiv_mask;
-		write32(param->refdiv_addr, reg);
+		write32_x(param->refdiv_addr, reg);
 	}
 
 	/* Read postdivider register value */
-	reg = read32(param->postdiv_addr);
+	reg = read32_x(param->postdiv_addr);
 	/* Set divider 1 */
 	reg &= ~(param->postdiv1_mask);
 	reg |= (divider1 << param->postdiv1_shift) &
@@ -295,19 +295,19 @@ static int pll_setup(struct pll_parameters *param, u8 divider1, u8 divider2)
 	reg |= (divider2 << param->postdiv2_shift) &
 			param->postdiv2_mask;
 	/* Write back to register */
-	write32(param->postdiv_addr, reg);
+	write32_x(param->postdiv_addr, reg);
 
 	/* Waiting for PLL to lock*/
 	stopwatch_init_usecs_expire(&sw, PLL_TIMEOUT_VALUE_US);
-	while (!(read32(param->status_addr) & param->status_lock_mask)) {
+	while (!(read32_x(param->status_addr) & param->status_lock_mask)) {
 		if (stopwatch_expired(&sw))
 			return PLL_TIMEOUT;
 	}
 
 	/* Start using PLL */
-	reg = read32(PISTACHIO_CLOCK_SWITCH);
+	reg = read32_x(PISTACHIO_CLOCK_SWITCH);
 	reg |= param->external_bypass_mask;
-	write32(PISTACHIO_CLOCK_SWITCH, reg);
+	write32_x(PISTACHIO_CLOCK_SWITCH, reg);
 
 	return CLOCKS_OK;
 }
@@ -340,16 +340,16 @@ void uart1_clk_setup(u8 divider1, u16 divider2)
 	assert(!(divider2 & ~(UART1CLKOUT_MASK)));
 
 	/* Set divider 1 */
-	reg = read32(UART1CLKINTERNAL_CTRL_ADDR);
+	reg = read32_x(UART1CLKINTERNAL_CTRL_ADDR);
 	reg &= ~UART1CLKINTERNAL_MASK;
 	reg |= divider1 & UART1CLKINTERNAL_MASK;
-	write32(UART1CLKINTERNAL_CTRL_ADDR, reg);
+	write32_x(UART1CLKINTERNAL_CTRL_ADDR, reg);
 
 	/* Set divider 2 */
-	reg = read32(UART1CLKOUT_CTRL_ADDR);
+	reg = read32_x(UART1CLKOUT_CTRL_ADDR);
 	reg &= ~UART1CLKOUT_MASK;
 	reg |= divider2 & UART1CLKOUT_MASK;
-	write32(UART1CLKOUT_CTRL_ADDR, reg);
+	write32_x(UART1CLKOUT_CTRL_ADDR, reg);
 }
 
 /*
@@ -366,16 +366,16 @@ void i2c_clk_setup(u8 divider1, u16 divider2, u8 interface)
 	assert(!(divider2 & ~(I2CCLKOUT_MASK)));
 	assert(interface < 4);
 	/* Set divider 1 */
-	reg = read32(I2CCLKDIV1_CTRL_ADDR(interface));
+	reg = read32_x(I2CCLKDIV1_CTRL_ADDR(interface));
 	reg &= ~I2CCLKDIV1_MASK;
 	reg |= divider1 & I2CCLKDIV1_MASK;
-	write32(I2CCLKDIV1_CTRL_ADDR(interface), reg);
+	write32_x(I2CCLKDIV1_CTRL_ADDR(interface), reg);
 
 	/* Set divider 2 */
-	reg = read32(I2CCLKOUT_CTRL_ADDR(interface));
+	reg = read32_x(I2CCLKOUT_CTRL_ADDR(interface));
 	reg &= ~I2CCLKOUT_MASK;
 	reg |= divider2 & I2CCLKOUT_MASK;
-	write32(I2CCLKOUT_CTRL_ADDR(interface), reg);
+	write32_x(I2CCLKOUT_CTRL_ADDR(interface), reg);
 }
 
 /* system_clk_setup: sets up the system (peripheral) clock */
@@ -387,10 +387,10 @@ void system_clk_setup(u8 divider)
 	assert(!(divider & ~(SYSCLKINTERNAL_MASK)));
 
 	/* Set system clock divider */
-	reg = read32(SYSCLKINTERNAL_CTRL_ADDR);
+	reg = read32_x(SYSCLKINTERNAL_CTRL_ADDR);
 	reg &= ~SYSCLKINTERNAL_MASK;
 	reg |= divider & SYSCLKINTERNAL_MASK;
-	write32(SYSCLKINTERNAL_CTRL_ADDR, reg);
+	write32_x(SYSCLKINTERNAL_CTRL_ADDR, reg);
 
 	/* Small delay to cover a maximum lock time of 1500 cycles */
 	udelay(SYS_CLK_LOCK_DELAY);
@@ -405,16 +405,16 @@ void mips_clk_setup(u8 divider1, u8 divider2)
 	assert(!(divider2 & ~(MIPSCLKOUT_MASK)));
 
 	/* Set divider 1 */
-	reg = read32(MIPSCLKINTERNAL_CTRL_ADDR);
+	reg = read32_x(MIPSCLKINTERNAL_CTRL_ADDR);
 	reg &= ~MIPSCLKINTERNAL_MASK;
 	reg |= divider1 & MIPSCLKINTERNAL_MASK;
-	write32(MIPSCLKINTERNAL_CTRL_ADDR, reg);
+	write32_x(MIPSCLKINTERNAL_CTRL_ADDR, reg);
 
 	/* Set divider 2 */
-	reg = read32(MIPSCLKOUT_CTRL_ADDR);
+	reg = read32_x(MIPSCLKOUT_CTRL_ADDR);
 	reg &= ~MIPSCLKOUT_MASK;
 	reg |= divider2 & MIPSCLKOUT_MASK;
-	write32(MIPSCLKOUT_CTRL_ADDR, reg);
+	write32_x(MIPSCLKOUT_CTRL_ADDR, reg);
 }
 
 /* usb_clk_setup: sets up USB clock */
@@ -431,29 +431,29 @@ int usb_clk_setup(u8 divider, u8 refclksel, u8 fsel)
 		~(USBPHYCONTROL1_FSEL_MASK)));
 
 	/* Set USB divider */
-	reg = read32(USBPHYCLKOUT_CTRL_ADDR);
+	reg = read32_x(USBPHYCLKOUT_CTRL_ADDR);
 	reg &= ~USBPHYCLKOUT_MASK;
 	reg |= divider & USBPHYCLKOUT_MASK;
-	write32(USBPHYCLKOUT_CTRL_ADDR, reg);
+	write32_x(USBPHYCLKOUT_CTRL_ADDR, reg);
 
 	/* Set REFCLKSEL */
-	reg = read32(USBPHYSTRAPCTRL_ADDR);
+	reg = read32_x(USBPHYSTRAPCTRL_ADDR);
 	reg &= ~USBPHYSTRAPCTRL_REFCLKSEL_MASK;
 	reg |= (refclksel << USBPHYSTRAPCTRL_REFCLKSEL_SHIFT) &
 		USBPHYSTRAPCTRL_REFCLKSEL_MASK;
-	write32(USBPHYSTRAPCTRL_ADDR, reg);
+	write32_x(USBPHYSTRAPCTRL_ADDR, reg);
 
 	/* Set FSEL */
-	reg = read32(USBPHYCONTROL1_ADDR);
+	reg = read32_x(USBPHYCONTROL1_ADDR);
 	reg &= ~USBPHYCONTROL1_FSEL_MASK;
 	reg |= (fsel << USBPHYCONTROL1_FSEL_SHIFT) &
 		USBPHYCONTROL1_FSEL_MASK;
-	write32(USBPHYCONTROL1_ADDR, reg);
+	write32_x(USBPHYCONTROL1_ADDR, reg);
 
 	/* Waiting for USB clock status */
 	stopwatch_init_usecs_expire(&sw, USB_TIMEOUT_VALUE_US);
 	while (1) {
-		reg = read32(USBPHYSTATUS_ADDR);
+		reg = read32_x(USBPHYSTATUS_ADDR);
 		if (reg & USBPHYSTATUS_VBUS_FAULT_MASK)
 			return USB_VBUS_FAULT;
 		if (stopwatch_expired(&sw))
@@ -475,10 +475,10 @@ void rom_clk_setup(u8 divider)
 	assert(!(divider & ~(ROMCLKOUT_MASK)));
 
 	/* Set ROM divider */
-	reg = read32(ROMCLKOUT_CTRL_ADDR);
+	reg = read32_x(ROMCLKOUT_CTRL_ADDR);
 	reg &= ~ROMCLKOUT_MASK;
 	reg |= divider & ROMCLKOUT_MASK;
-	write32(ROMCLKOUT_CTRL_ADDR, reg);
+	write32_x(ROMCLKOUT_CTRL_ADDR, reg);
 }
 
 void eth_clk_setup(u8 mux, u8 divider)
@@ -493,21 +493,21 @@ void eth_clk_setup(u8 mux, u8 divider)
 	assert(!(mux & ~(0x1)));
 
 	/* Set ETH divider */
-	reg = read32(ENETCLKDIV_CTRL_ADDR);
+	reg = read32_x(ENETCLKDIV_CTRL_ADDR);
 	reg &= ~ENETCLKDIV_MASK;
 	reg |= divider & ENETCLKDIV_MASK;
-	write32(ENETCLKDIV_CTRL_ADDR, reg);
+	write32_x(ENETCLKDIV_CTRL_ADDR, reg);
 
 	/* Select source */
 	if (mux) {
-		reg = read32(PISTACHIO_CLOCK_SWITCH);
+		reg = read32_x(PISTACHIO_CLOCK_SWITCH);
 		reg |= ENETCLKMUX_MASK;
-		write32(PISTACHIO_CLOCK_SWITCH, reg);
+		write32_x(PISTACHIO_CLOCK_SWITCH, reg);
 	}
 }
 
 void setup_clk_gate_defaults(void)
 {
-	write32(MIPS_CLOCK_GATE_ADDR, MIPS_CLOCK_GATE_ALL_ON);
-	write32(RPU_CLOCK_GATE_ADDR, RPU_CLOCK_GATE_ALL_OFF);
+	write32_x(MIPS_CLOCK_GATE_ADDR, MIPS_CLOCK_GATE_ALL_ON);
+	write32_x(RPU_CLOCK_GATE_ADDR, RPU_CLOCK_GATE_ALL_OFF);
 }
diff --git a/src/soc/imgtec/pistachio/ddr2_init.c b/src/soc/imgtec/pistachio/ddr2_init.c
index e05fda5b5c..39b553df24 100644
--- a/src/soc/imgtec/pistachio/ddr2_init.c
+++ b/src/soc/imgtec/pistachio/ddr2_init.c
@@ -33,31 +33,31 @@ int init_ddr2(void)
 	 * writes have already happened to DDR - note must be done together,
 	 * not sequentially
 	 */
-	write32(TOPLEVEL_REGS + DDR_CTRL_OFFSET, 0x00000000);
-	write32(TOPLEVEL_REGS + DDR_CTRL_OFFSET, 0x0000000F);
+	write32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET, 0x00000000);
+	write32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET, 0x0000000F);
 	/*
 	 * Dummy read to fence the access between the reset above
 	 * and thw DDR controller writes below
 	 */
-	read32(TOPLEVEL_REGS + DDR_CTRL_OFFSET);
+	read32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET);
 	/* Timings for 400MHz
 	 * therefore 200MHz (5ns) uMCTL (Internal) Rate
 	 */
 	/* TOGCNT1U: Toggle Counter 1U Register: 1us 200h C8h */
-	write32(DDR_PCTL + DDR_PCTL_TOGCNT1U_OFFSET, 0x000000C8);
+	write32_x(DDR_PCTL + DDR_PCTL_TOGCNT1U_OFFSET, 0x000000C8);
 	/* TINIT: t_init Timing Register: at least 200us 200h C8h */
-	write32(DDR_PCTL + DDR_PCTL_TINIT_OFFSET, 0x000000C8);
+	write32_x(DDR_PCTL + DDR_PCTL_TINIT_OFFSET, 0x000000C8);
 	/* TRSTH: Reset High Time Register DDR3 ONLY */
-	write32(DDR_PCTL + DDR_PCTL_TRSTH_OFFSET, 0x00000000);
+	write32_x(DDR_PCTL + DDR_PCTL_TRSTH_OFFSET, 0x00000000);
 	/* TOGCNT100N: Toggle Counter 100N Register: 20d, 14h*/
-	write32(DDR_PCTL + DDR_PCTL_TOGG_CNTR_100NS_OFFSET, 0x00000014);
+	write32_x(DDR_PCTL + DDR_PCTL_TOGG_CNTR_100NS_OFFSET, 0x00000014);
 	/* DTUAWDT DTU Address Width Register
 	 * 1:0   column_addr_width Def 10 - 7  3 10 bits
 	 * 4:3   bank_addr_width   Def  3 - 2  1  3 bits (8 bank)
 	 * 7:6   row_addr_width    Def 14 - 13 1  3 bits
 	 * 10:9  number_ranks      Def  1 -  1 0  0 1 Rank
 	 */
-	write32(DDR_PCTL + DDR_PCTL_DTUAWDT_OFFSET, 0x0000004B);
+	write32_x(DDR_PCTL + DDR_PCTL_DTUAWDT_OFFSET, 0x0000004B);
 	/* MCFG
 	 * 0 BL 0 = 4 1 = 8
 	 * 1 RDRIMM 0
@@ -75,7 +75,7 @@ int init_ddr2(void)
 	 * 23:22 mDDR/LPDDR2 Enable 0
 	 * 31:24 mDDR/LPDDR2/3 Dynamic Clock Stop 0
 	 */
-	write32(DDR_PCTL + DDR_PCTL_MCFG_OFFSET,
+	write32_x(DDR_PCTL + DDR_PCTL_MCFG_OFFSET,
 		0x00060000 | (BL8 ? 0x1 : 0x0));
 	/* MCFG1: Memory Configuration-1 Register
 	 * c7:0 sr_idle Self Refresh Idle Entery 32 * nclks 14h, set 0 for BUB
@@ -85,7 +85,7 @@ int init_ddr2(void)
 	 * 30:24 Reserved
 	 * 31 c_active_in_pin exit auto clk stop NA 0
 	 */
-	write32(DDR_PCTL + DDR_PCTL_MCFG1_OFFSET, 0x00000100);
+	write32_x(DDR_PCTL + DDR_PCTL_MCFG1_OFFSET, 0x00000100);
 	/* DCR DRAM Config
 	 * 2:0 SDRAM => DDR2 2
 	 * 3 DDR 8 Bank 1
@@ -99,7 +99,7 @@ int init_ddr2(void)
 	 * 30 RDIMM NA 0
 	 * 31 TPD LPDDR2 0
 	 */
-	write32(DDR_PHY + DDRPHY_DCR_OFFSET, 0x0000000A);
+	write32_x(DDR_PHY + DDRPHY_DCR_OFFSET, 0x0000000A);
 	/* Generate to use with PHY and PCTL
 	 * MR0 : MR Register, bits 12:0 imported dfrom MR
 	 * 2:0 BL 8 011
@@ -112,7 +112,7 @@ int init_ddr2(void)
 	 * 15:13 RSVD RSVD
 	 * 31:16 Reserved
 	 */
-	write32(DDR_PHY + DDRPHY_MR_OFFSET, 0x00000B62 | (BL8 ? 0x1 : 0x0));
+	write32_x(DDR_PHY + DDRPHY_MR_OFFSET, 0x00000B62 | (BL8 ? 0x1 : 0x0));
 	/* MR1 : EMR Register
 	 * Generate to use with PHY and PCTL
 	 * 0 DE DLL Enable 0 Disable 1
@@ -126,7 +126,7 @@ int init_ddr2(void)
 	 * 15:13 RSVD
 	 * 31:16 Reserved
 	 */
-	write32(DDR_PHY + DDRPHY_EMR_OFFSET, 0x00000044);
+	write32_x(DDR_PHY + DDRPHY_EMR_OFFSET, 0x00000044);
 	/* MR2 : EMR2 Register
 	 * Generate to use with PHY and PCTL
 	 * 2:0 PASR, NA 000
@@ -136,7 +136,7 @@ int init_ddr2(void)
 	 * 15:8 RSVD
 	 * 31:16 Reserved
 	 */
-	write32(DDR_PHY + DDRPHY_EMR2_OFFSET, 0x00000000);
+	write32_x(DDR_PHY + DDRPHY_EMR2_OFFSET, 0x00000000);
 	/* DSGCR
 	 * 0 PUREN Def 1
 	 * 1 BDISEN Def 1
@@ -159,9 +159,9 @@ int init_ddr2(void)
 	 * 30 RSTOE RST# Output Enable 1
 	 * 31 CKEOE CKE Output Enable 1
 	 */
-	write32(DDR_PHY + DDRPHY_DSGCR_OFFSET, 0xF2000927);
+	write32_x(DDR_PHY + DDRPHY_DSGCR_OFFSET, 0xF2000927);
 	/* Sysnopsys advised 500R pullup/pulldown DQS DQSN */
-	write32(DDR_PHY + DDRPHY_DXCCR_OFFSET, 0x00000C40);
+	write32_x(DDR_PHY + DDRPHY_DXCCR_OFFSET, 0x00000C40);
 	/* DTPR0 : DRAM Timing Params 0
 	 * 1:0 tMRD 2
 	 * 4:2 tRTP 3
@@ -173,7 +173,7 @@ int init_ddr2(void)
 	 * 30:25 tRC 24 (23)
 	 * 31 tCCD 0 BL/2 Cas to Cas
 	 */
-	write32(DDR_PHY + DDRPHY_DTPR0_OFFSET, 0x3092666E);
+	write32_x(DDR_PHY + DDRPHY_DTPR0_OFFSET, 0x3092666E);
 	/* DTPR1 : DRAM Timing Params 1
 	 * 1:0 ODT On/Off Del Std 0
 	 * 2 tRTW Rd2Wr Del 0 std 1 +1 0
@@ -186,7 +186,7 @@ int init_ddr2(void)
 	 * 29:27 tDQSCKmax 1
 	 * 31:30 Reserved
 	 */
-	write32(DDR_PHY + DDRPHY_DTPR1_OFFSET, 0x094E0092);
+	write32_x(DDR_PHY + DDRPHY_DTPR1_OFFSET, 0x094E0092);
 	/* DTPR2 : DRAM Timing Params 2
 	 * 9:0 tXS exit SR def 200, 200d
 	 * 14:10 tXP PD Exit Del 8 3
@@ -194,19 +194,19 @@ int init_ddr2(void)
 	 * 28:19 tDLLK DLL Lock time 200d
 	 * 32:29 Reserved
 	 */
-	write32(DDR_PHY + DDRPHY_DTPR2_OFFSET, 0x06418CC8);
+	write32_x(DDR_PHY + DDRPHY_DTPR2_OFFSET, 0x06418CC8);
 	/* PTR0 : PHY Timing Params 0
 	 * 5:0 tDLLRST Def 27
 	 * 17:6 tDLLLOCK Def 2750
 	 * 21:18 tITMSRST Def 8
 	 * 31:22 Reserved 0
 	 */
-	write32(DDR_PHY + DDRPHY_PTR0_OFFSET, 0x0022AF9B);
+	write32_x(DDR_PHY + DDRPHY_PTR0_OFFSET, 0x0022AF9B);
 	/* PTR1 : PHY Timing Params 1
 	 * 18:0 : tDINITO DRAM Init time 200us 80,000 Dec 0x13880
 	 * 29:19 : tDINIT1 DRAM Init time 400ns 160 Dec 0xA0
 	 */
-	write32(DDR_PHY + DDRPHY_PTR1_OFFSET, 0x05013880);
+	write32_x(DDR_PHY + DDRPHY_PTR1_OFFSET, 0x05013880);
 	/* DQS gating configuration: passive windowing mode */
 	/*
 	 * PGCR: PHY General cofiguration register
@@ -228,25 +228,25 @@ int init_ddr2(void)
 	 * 30 loopback DQS gating 0
 	 * 31 loopback mode 0
 	 */
-	write32(DDR_PHY + DDRPHY_PGCR_OFFSET, 0x01BC2E02);
+	write32_x(DDR_PHY + DDRPHY_PGCR_OFFSET, 0x01BC2E02);
 	/* PGSR : Wait for INIT/DLL/Z Done from Power on Reset */
 	if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x00000007))
 		return DDR_TIMEOUT;
 	/* PIR : use PHY for DRAM Init */
-	write32(DDR_PHY + DDRPHY_PIR_OFFSET, 0x000001DF);
+	write32_x(DDR_PHY + DDRPHY_PIR_OFFSET, 0x000001DF);
 	/* PGSR : Wait for DRAM Init Done */
 	if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x0000001F))
 			return DDR_TIMEOUT;
 	/* Disable Impedance Calibration */
-	write32(DDR_PHY + DDRPHY_ZQ0CR0_OFFSET, 0x3000014A);
-	write32(DDR_PHY + DDRPHY_ZQ1CR0_OFFSET, 0x3000014A);
+	write32_x(DDR_PHY + DDRPHY_ZQ0CR0_OFFSET, 0x3000014A);
+	write32_x(DDR_PHY + DDRPHY_ZQ1CR0_OFFSET, 0x3000014A);
 
 	/* DF1STAT0 : wait for DFI_INIT_COMPLETE */
 	if (wait_for_completion(DDR_PCTL + DDR_PCTL_DFISTAT0_OFFSET,
 						0x00000001))
 		return DDR_TIMEOUT;
 	/* POWCTL : Start the memory Power Up seq*/
-	write32(DDR_PCTL + DDR_PCTL_POWCTL_OFFSET, 0x00000001);
+	write32_x(DDR_PCTL + DDR_PCTL_POWCTL_OFFSET, 0x00000001);
 	/* POWSTAT : wait for POWER_UP_DONE */
 	if (wait_for_completion(DDR_PCTL + DDR_PCTL_POWSTAT_OFFSET,
 						0x00000001))
@@ -259,84 +259,84 @@ int init_ddr2(void)
 	 * 30:19 Reserved 0
 	 * 31 Update 1
 	 */
-	write32(DDR_PCTL + DDR_PCTL_TREFI_OFFSET, 0x8000004E);
+	write32_x(DDR_PCTL + DDR_PCTL_TREFI_OFFSET, 0x8000004E);
 	/* TMRD : t_mrd Timing Register -- Range 2 to 3 */
-	write32(DDR_PCTL + DDR_PCTL_TMRD_OFFSET, 0x00000002);
+	write32_x(DDR_PCTL + DDR_PCTL_TMRD_OFFSET, 0x00000002);
 	/*
 	 * TRFC : t_rfc Timing Register -- Range 15 to 131
 	 * 195ns / 2.5ns 78 x4E
 	 */
-	write32(DDR_PCTL + DDR_PCTL_TRFC_OFFSET, 0x0000004E);
+	write32_x(DDR_PCTL + DDR_PCTL_TRFC_OFFSET, 0x0000004E);
 	/* TRP : t_rp Timing Register -- Range 3 to 7
 	 * 4:0 tRP 12.5 / 2.5 = 5 6 For Now 6-6-6
 	 * 17:16 rpea_extra tRPall 8 bank 1
 	 */
-	write32(DDR_PCTL + DDR_PCTL_TRP_OFFSET, 0x00010006);
+	write32_x(DDR_PCTL + DDR_PCTL_TRP_OFFSET, 0x00010006);
 	/* TAL : Additive Latency Register -- AL in MR1 */
-	write32(DDR_PCTL + DDR_PCTL_TAL_OFFSET, 0x00000000);
+	write32_x(DDR_PCTL + DDR_PCTL_TAL_OFFSET, 0x00000000);
 	/* DFITPHYWRLAT : Write cmd to dfi_wrdata_en */
-	write32(DDR_PCTL + DDR_PCTL_DFIWRLAT_OFFSET, 0x00000002);
+	write32_x(DDR_PCTL + DDR_PCTL_DFIWRLAT_OFFSET, 0x00000002);
 	/* DFITRDDATAEN : Read cmd to dfi_rddata_en */
-	write32(DDR_PCTL + DDR_PCTL_DFITRDDATAEN_OFFSET, 0x00000002);
+	write32_x(DDR_PCTL + DDR_PCTL_DFITRDDATAEN_OFFSET, 0x00000002);
 	/* TCL : CAS Latency Timing Register -- CASL in MR0 6-6-6 */
-	write32(DDR_PCTL + DDR_PCTL_TCL_OFFSET, 0x00000006);
+	write32_x(DDR_PCTL + DDR_PCTL_TCL_OFFSET, 0x00000006);
 	/* TCWL : CAS Write Latency Register --CASL-1 */
-	write32(DDR_PCTL + DDR_PCTL_TCWL_OFFSET, 0x00000005);
+	write32_x(DDR_PCTL + DDR_PCTL_TCWL_OFFSET, 0x00000005);
 	/*
 	 * TRAS : Activate to Precharge cmd time
 	 * Range 8 to 24: 45ns / 2.5ns = 18d
 	 */
-	write32(DDR_PCTL + DDR_PCTL_TRAS_OFFSET, 0x00000012);
+	write32_x(DDR_PCTL + DDR_PCTL_TRAS_OFFSET, 0x00000012);
 	/*
 	 * TRC : Min. ROW cycle time
 	 * Range 11 to 31: 57.5ns / 2.5ns = 23d Playing safe 24
 	 */
-	write32(DDR_PCTL + DDR_PCTL_TRC_OFFSET, 0x00000018);
+	write32_x(DDR_PCTL + DDR_PCTL_TRC_OFFSET, 0x00000018);
 	/*
 	 * TRCD : Row to Column Delay
 	 * Range 3 to 7 (TCL = TRCD): 2.5ns / 2.5ns = 5 but running 6-6-6 6
 	 */
-	write32(DDR_PCTL + DDR_PCTL_TRCD_OFFSET, 0x00000006);
+	write32_x(DDR_PCTL + DDR_PCTL_TRCD_OFFSET, 0x00000006);
 	/* TRRD : Row to Row delay -- Range 2 to 6: 2K Page 10ns / 2.5ns = 4*/
-	write32(DDR_PCTL + DDR_PCTL_TRRD_OFFSET, 0x00000004);
+	write32_x(DDR_PCTL + DDR_PCTL_TRRD_OFFSET, 0x00000004);
 	/* TRTP : Read to Precharge time -- Range 2 to 4: 7.3ns / 2.5ns = 3 */
-	write32(DDR_PCTL + DDR_PCTL_TRTP_OFFSET, 0x00000003);
+	write32_x(DDR_PCTL + DDR_PCTL_TRTP_OFFSET, 0x00000003);
 	/* TWR : Write recovery time -- WR in MR0: 15ns / 2.5ns = 6
 	 */
-	write32(DDR_PCTL + DDR_PCTL_TWR_OFFSET, 0x00000006);
+	write32_x(DDR_PCTL + DDR_PCTL_TWR_OFFSET, 0x00000006);
 	/*
 	 * TWTR : Write to read turn around time
 	 * Range 2 to 4: 7.3ns / 2.5ns = 3
 	 */
-	write32(DDR_PCTL + DDR_PCTL_TWTR_OFFSET, 0x00000003);
+	write32_x(DDR_PCTL + DDR_PCTL_TWTR_OFFSET, 0x00000003);
 	/* TEXSR : Exit Self Refresh to first valid cmd: tXS 200*/
-	write32(DDR_PCTL + DDR_PCTL_TEXSR_OFFSET, 0x000000C8);
+	write32_x(DDR_PCTL + DDR_PCTL_TEXSR_OFFSET, 0x000000C8);
 	/*
 	 * TXP : Exit Power Down to first valid cmd
 	 * tXP 2, Settingto 3 to match PHY
 	 */
-	write32(DDR_PCTL + DDR_PCTL_TXP_OFFSET, 0x00000003);
+	write32_x(DDR_PCTL + DDR_PCTL_TXP_OFFSET, 0x00000003);
 	/*
 	 * TDQS : t_dqs Timing Register
 	 * DQS additional turn around Rank 2 Rank (1 Rank) Def 1
 	 */
-	write32(DDR_PCTL + DDR_PCTL_TDQS_OFFSET, 0x00000001);
+	write32_x(DDR_PCTL + DDR_PCTL_TDQS_OFFSET, 0x00000001);
 	/*TRTW : Read to Write turn around time Def 3
 	 * Actual gap t_bl + t_rtw
 	 */
-	write32(DDR_PCTL + DDR_PCTL_TRTW_OFFSET, 0x00000003);
+	write32_x(DDR_PCTL + DDR_PCTL_TRTW_OFFSET, 0x00000003);
 	/* TCKE : CKE min pulse width DEf 3 */
-	write32(DDR_PCTL + DDR_PCTL_TCKE_OFFSET, 0x00000003);
+	write32_x(DDR_PCTL + DDR_PCTL_TCKE_OFFSET, 0x00000003);
 	/*
 	 * TXPDLL : Slow Exit Power Down to first valid cmd delay
 	 * tXARDS 10+AL = 10
 	 */
-	write32(DDR_PCTL + DDR_PCTL_TXPDLL_OFFSET, 0x0000000A);
+	write32_x(DDR_PCTL + DDR_PCTL_TXPDLL_OFFSET, 0x0000000A);
 	/*
 	 * TCKESR : Min CKE Low width for Self refresh entry to exit
 	 * t_ckesr = 0 DDR2
 	 */
-	write32(DDR_PCTL + DDR_PCTL_TCKESR_OFFSET, 0x00000000);
+	write32_x(DDR_PCTL + DDR_PCTL_TCKESR_OFFSET, 0x00000000);
 	/* SCFG : State Configuration Register (Enabling Self Refresh)
 	 * 0 LP_en Leave Off for Bring Up 0
 	 * 5:1 Reserved
@@ -346,17 +346,17 @@ int init_ddr2(void)
 	 * 16:12 Additional delay on accertion of ac_pdd 4
 	 * 31:17 Reserved
 	 */
-	write32(DDR_PCTL + DDR_PCTL_SCFG_OFFSET, 0x00004480);
+	write32_x(DDR_PCTL + DDR_PCTL_SCFG_OFFSET, 0x00004480);
 	/*
 	 * DFITPHYWRDATA : dfi_wrdata_en to drive wr data
 	 * DFI Clks wrdata_en to wrdata Def 1
 	 */
-	write32(DDR_PCTL + DDR_PCTL_DFITPHYWRDATA_OFFSET, 0x00000000);
+	write32_x(DDR_PCTL + DDR_PCTL_DFITPHYWRDATA_OFFSET, 0x00000000);
 	/*
 	 * DFITPHYRDLAT : dfi_rddata_en to dfi_rddata_valid
 	 * DFI clks max rddata_en to rddata_valid Def 15
 	 */
-	write32(DDR_PCTL + DDR_PCTL_DFITPHYRDLAT_OFFSET, 0x00000008);
+	write32_x(DDR_PCTL + DDR_PCTL_DFITPHYRDLAT_OFFSET, 0x00000008);
 	/* MCMD : PREA, Addr 0 Bank 0 Rank 0 Del 0
 	 * 3:0 cmd_opcode PREA 00001
 	 * 16:4 cmd_addr 0
@@ -365,12 +365,12 @@ int init_ddr2(void)
 	 * 27:24 cmddelay 0
 	 * 30:24 Reserved
 	 */
-	write32(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80100001);
+	write32_x(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80100001);
 	/* MRS cmd wait for completion */
 	if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00100001))
 		return DDR_TIMEOUT;
 	/* SCTL : UPCTL switch INIT CONFIG State */
-	write32(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000001);
+	write32_x(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000001);
 	/* STAT : Wait for Switch INIT to Config State */
 	if (wait_for_completion(DDR_PCTL + DDR_PCTL_STAT_OFFSET, 0x00000001))
 		return DDR_TIMEOUT;
@@ -379,17 +379,17 @@ int init_ddr2(void)
 	 * 1 dfi_freq_ratio_en         1
 	 * 2 dfi_data_byte_disable_en  1
 	 */
-	write32(DDR_PCTL + DDR_PCTL_DFISTCFG0_OFFSET, 0x00000003);
+	write32_x(DDR_PCTL + DDR_PCTL_DFISTCFG0_OFFSET, 0x00000003);
 	/* DFISTCFG1 : Enable various DFI support
 	 * 0 dfi_dram_clk_disable_en 1
 	 * 1 dfi_dram_clk_disable_en_pdp only lPDDR 0
 	 */
-	write32(DDR_PCTL + DDR_PCTL_DFISTCFG1_OFFSET, 0x00000001);
+	write32_x(DDR_PCTL + DDR_PCTL_DFISTCFG1_OFFSET, 0x00000001);
 	/* DFISTCFG2 : Enable Parity and asoc interrupt
 	 * 0 dfi_parity_in Enable 1
 	 * 1 Interrupt on dfi_parity_error 1
 	 */
-	write32(DDR_PCTL + DDR_PCTL_DFISTCFG2_OFFSET, 0x00000003);
+	write32_x(DDR_PCTL + DDR_PCTL_DFISTCFG2_OFFSET, 0x00000003);
 	/* DFILPCFG0 : DFI Low Power Interface Configuration
 	 * 0     Enable DFI LP IF during PD 1
 	 * 3:1   Reserved
@@ -403,7 +403,7 @@ int init_ddr2(void)
 	 * 27:25 Reserved
 	 * 31:28 DFI LP Deep Power Down Value 0
 	 */
-	write32(DDR_PCTL + DDR_PCTL_DFILPCFG0_OFFSET, 0x00070101);
+	write32_x(DDR_PCTL + DDR_PCTL_DFILPCFG0_OFFSET, 0x00070101);
 	/* DFIODTCFG : DFI ODT Configuration
 	 * Only Enabled on Rank0 Writes
 	 * 0 rank0_odt_read_nsel  0
@@ -411,14 +411,14 @@ int init_ddr2(void)
 	 * 2 rank0_odt_write_nsel 0
 	 * 3 rank0_odt_write_sel  1
 	 */
-	write32(DDR_PCTL + DDR_PCTL_DFIODTCFG_OFFSET, 0x00000008);
+	write32_x(DDR_PCTL + DDR_PCTL_DFIODTCFG_OFFSET, 0x00000008);
 	/* DFIODTCFG1 : DFI ODT Configuration
 	 * 4:0   odt_lat_w     4
 	 * 12:8  odt_lat_r     0 Def
 	 * 4:0   odt_len_bl8_w 6 Def
 	 * 12:8  odt_len_bl8_r 6 Def
 	 */
-	write32(DDR_PCTL + DDR_PCTL_DFIODTCFG1_OFFSET, 0x06060004);
+	write32_x(DDR_PCTL + DDR_PCTL_DFIODTCFG1_OFFSET, 0x06060004);
 	/* DCFG : DRAM Density 256 Mb 16 Bit IO Width
 	 * 1:0  Devicw Width 1 x8, 2 x16, 3 x32  2
 	 * 5:2  Density 2Gb = 5
@@ -427,14 +427,14 @@ int init_ddr2(void)
 	 * 10:8 Address Map R/B/C = 1
 	 * 31:11 Reserved
 	 */
-	write32(DDR_PCTL + DDR_PCTL_DCFG_OFFSET, 0x00000116);
+	write32_x(DDR_PCTL + DDR_PCTL_DCFG_OFFSET, 0x00000116);
 	/* PCFG_0 : Port 0 AXI config  */
 	if (BL8)
-		write32(DDR_PCTL + DDR_PCTL_PCFG0_OFFSET, 0x000800A0);
+		write32_x(DDR_PCTL + DDR_PCTL_PCFG0_OFFSET, 0x000800A0);
 	else
-		write32(DDR_PCTL + DDR_PCTL_PCFG0_OFFSET, 0x000400A0);
+		write32_x(DDR_PCTL + DDR_PCTL_PCFG0_OFFSET, 0x000400A0);
 	/* SCTL : UPCTL switch Config to ACCESS State */
-	write32(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000002);
+	write32_x(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000002);
 	/* STAT : Wait for switch CFG -> GO State */
 	if (wait_for_completion(DDR_PCTL + DDR_PCTL_STAT_OFFSET, 0x3))
 		return DDR_TIMEOUT;
diff --git a/src/soc/imgtec/pistachio/ddr3_init.c b/src/soc/imgtec/pistachio/ddr3_init.c
index 2effb8b2d8..7392525d23 100644
--- a/src/soc/imgtec/pistachio/ddr3_init.c
+++ b/src/soc/imgtec/pistachio/ddr3_init.c
@@ -27,45 +27,45 @@ int init_ddr3(void)
 {
 	uint32_t temp_rw_val;
 
-	temp_rw_val = read32(TOPLEVEL_REGS + DDR_CTRL_OFFSET);
+	temp_rw_val = read32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET);
 	/* Set CLK_EN = 1 */
 	temp_rw_val |= 0x2;
-	write32(TOPLEVEL_REGS + DDR_CTRL_OFFSET, temp_rw_val);
-	read32(TOPLEVEL_REGS + DDR_CTRL_OFFSET);
+	write32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET, temp_rw_val);
+	read32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET);
 	/*
 	 * Reset the AXI bridge and DDR Controller in case any spurious
 	 * writes have already happened to DDR
 	 */
 	/* Drive the 3 resets low */
-	write32(TOPLEVEL_REGS + DDR_CTRL_OFFSET, 0x00000002);
-	read32(TOPLEVEL_REGS + DDR_CTRL_OFFSET);
-	read32(TOPLEVEL_REGS + DDR_CTRL_OFFSET);
+	write32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET, 0x00000002);
+	read32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET);
+	read32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET);
 
 	/* And release */
-	write32(TOPLEVEL_REGS + DDR_CTRL_OFFSET, 0x0000000F);
+	write32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET, 0x0000000F);
 	/* Dummy read to fence the access between the reset above and
 	 * the DDR controller writes below
 	 */
-	read32(TOPLEVEL_REGS + DDR_CTRL_OFFSET);
+	read32_x(TOPLEVEL_REGS + DDR_CTRL_OFFSET);
 
 	/* Timings for 400MHz
 	 * therefore 200MHz (5ns) uMCTL (Internal) Rate
 	 */
 	/* TOGCNT1U: Toggle Counter 1U Register: 1us 200h C8h */
-	write32(DDR_PCTL + DDR_PCTL_TOGCNT1U_OFFSET, 0x000000C8);
+	write32_x(DDR_PCTL + DDR_PCTL_TOGCNT1U_OFFSET, 0x000000C8);
 	/* TINIT: t_init Timing Register: at least 200us 200h C8h */
-	write32(DDR_PCTL + DDR_PCTL_TINIT_OFFSET, 0x000000C8);
+	write32_x(DDR_PCTL + DDR_PCTL_TINIT_OFFSET, 0x000000C8);
 	/* TRSTH: Reset High Time Register DDR3 ONLY */
-	write32(DDR_PCTL + DDR_PCTL_TRSTH_OFFSET, 0x000001F4);
+	write32_x(DDR_PCTL + DDR_PCTL_TRSTH_OFFSET, 0x000001F4);
 	/* TOGCNT100N: Toggle Counter 100N Register: 20d, 14h*/
-	write32(DDR_PCTL + DDR_PCTL_TOGG_CNTR_100NS_OFFSET, 0x00000014);
+	write32_x(DDR_PCTL + DDR_PCTL_TOGG_CNTR_100NS_OFFSET, 0x00000014);
 	/* DTUAWDT DTU Address Width Register
 	 * 1:0   column_addr_width Def 10 - 7  3 10 bits
 	 * 4:3   bank_addr_width   Def  3 - 2  1  3 bits (8 bank)
 	 * 7:6   row_addr_width    Def 14 - 13 1  3 bits
 	 * 10:9  number_ranks      Def  1 -  1 0  0 1 Rank
 	 */
-	write32(DDR_PCTL + DDR_PCTL_DTUAWDT_OFFSET, 0x0000004B);
+	write32_x(DDR_PCTL + DDR_PCTL_DTUAWDT_OFFSET, 0x0000004B);
 	/* MCFG
 	 * 0 BL 1 -> 8 fixed
 	 * 1 RDRIMM 0
@@ -83,7 +83,7 @@ int init_ddr3(void)
 	 * 23:22 mDDR/LPDDR2 Enable 0
 	 * 31:24 mDDR/LPDDR2/3 Dynamic Clock Stop 0
 	 */
-	write32(DDR_PCTL + DDR_PCTL_MCFG_OFFSET, 0x00060021);
+	write32_x(DDR_PCTL + DDR_PCTL_MCFG_OFFSET, 0x00060021);
 	/* MCFG1: Memory Configuration-1 Register
 	 * c7:0 sr_idle Self Refresh Idle Entery 32 * nclks 14h, set 0 for BUB
 	 * 10:8 Fine tune MCFG.19:18 -1
@@ -92,7 +92,7 @@ int init_ddr3(void)
 	 * 30:24 Reserved
 	 * 31 c_active_in_pin exit auto clk stop NA 0
 	 */
-	write32(DDR_PCTL + DDR_PCTL_MCFG1_OFFSET, 0x00000100);
+	write32_x(DDR_PCTL + DDR_PCTL_MCFG1_OFFSET, 0x00000100);
 	/* DCR DRAM Config
 	 * 2:0 SDRAM => DDR3 3
 	 * 3 DDR 8 Bank 1
@@ -106,7 +106,7 @@ int init_ddr3(void)
 	 * 30 RDIMM NA 0
 	 * 31 TPD LPDDR2 0
 	 */
-	write32(DDR_PHY + DDRPHY_DCR_OFFSET, 0x0000000B);
+	write32_x(DDR_PHY + DDRPHY_DCR_OFFSET, 0x0000000B);
 	/* Generate to use with PHY and PCTL
 	 * MR0 : DDR3 mode register 0
 	 * 1:0 BL 8 fixed 00
@@ -119,7 +119,7 @@ int init_ddr3(void)
 	 * 15:13 RSVD RSVD
 	 * 31:16 Reserved
 	 */
-	write32(DDR_PHY + DDRPHY_MR_OFFSET, 0x00001520);
+	write32_x(DDR_PHY + DDRPHY_MR_OFFSET, 0x00001520);
 	/* MR1 : DDR3 mode register 1
 	 * Generate to use with PHY and PCTL
 	 * 0 DE DLL Enable 0 Disable 1
@@ -133,7 +133,7 @@ int init_ddr3(void)
 	 * 15:13 RSVD
 	 * 31:16 Reserved
 	 */
-	write32(DDR_PHY + DDRPHY_EMR_OFFSET, 0x00000004);
+	write32_x(DDR_PHY + DDRPHY_EMR_OFFSET, 0x00000004);
 	/* MR2 : DDR3 mode register 2
 	 * Generate to use with PHY and PCTL
 	 * 2:0 PASR, NA 000
@@ -144,19 +144,19 @@ int init_ddr3(void)
 	 * 10:9 dynamic ODT 10 RZQ/2
 	 * 31:11 Reserved
 	 */
-	write32(DDR_PHY + DDRPHY_EMR2_OFFSET, 0x00000440);
+	write32_x(DDR_PHY + DDRPHY_EMR2_OFFSET, 0x00000440);
 	/* MR3: DDR3 mode register 3
 	 * 1:0 MPRLOC 00
 	 * 2 MPR 0
 	 */
-	write32(DDR_PHY + DDRPHY_EMR3_OFFSET, 0x00000000);
+	write32_x(DDR_PHY + DDRPHY_EMR3_OFFSET, 0x00000000);
 	/* DTAR : Data Training Register
 	 * 11:0  Data Training Column Address
 	 * 27:12 Data Training Row Address
 	 * 30:28 Data Training Bank Address
 	 * 31    Data Training Use MPR (DDR3 Only)
 	 */
-	write32(DDR_PHY + DDRPHY_DTAR_OFFSET, 0x00000000);
+	write32_x(DDR_PHY + DDRPHY_DTAR_OFFSET, 0x00000000);
 	/* DSGCR
 	 * 0 PUREN Def 1
 	 * 1 BDISEN Def 1
@@ -179,9 +179,9 @@ int init_ddr3(void)
 	 * 30 RSTOE RST# Output Enable 1
 	 * 31 CKEOE CKE Output Enable 1
 	 */
-	write32(DDR_PHY + DDRPHY_DSGCR_OFFSET, 0xFA000927);
+	write32_x(DDR_PHY + DDRPHY_DSGCR_OFFSET, 0xFA000927);
 	/* Sysnopsys advised 500R pullup/pulldown DQS DQSN */
-	write32(DDR_PHY + DDRPHY_DXCCR_OFFSET, 0x00000C40);
+	write32_x(DDR_PHY + DDRPHY_DXCCR_OFFSET, 0x00000C40);
 	/* DTPR0 : DRAM Timing Params 0
 	 * 1:0 tMRD 0
 	 * 4:2 tRTP 2
@@ -193,7 +193,7 @@ int init_ddr3(void)
 	 * 30:25 tRC 21
 	 * 31 tCCD 0 BL/2 Cas to Cas
 	 */
-	write32(DDR_PHY + DDRPHY_DTPR0_OFFSET, 0x2A8F6688);
+	write32_x(DDR_PHY + DDRPHY_DTPR0_OFFSET, 0x2A8F6688);
 	/* DTPR1 : DRAM Timing Params 1
 	 * 1:0 ODT On/Off Del Std 0
 	 * 2 tRTW Rd2Wr Del 0 std 1 +1 0
@@ -206,7 +206,7 @@ int init_ddr3(void)
 	 * 29:27 tDQSCKmax 1
 	 * 31:30 Reserved
 	 */
-	write32(DDR_PHY + DDRPHY_DTPR1_OFFSET, 0x094006A0);
+	write32_x(DDR_PHY + DDRPHY_DTPR1_OFFSET, 0x094006A0);
 	/* DTPR2 : DRAM Timing Params 2
 	 * 9:0 tXS exit SR def 512d
 	 * 14:10 tXP PD Exit Del 8 5
@@ -214,19 +214,19 @@ int init_ddr3(void)
 	 * 28:19 tDLLK DLL Lock time 512d
 	 * 32:29 Reserved
 	 */
-	write32(DDR_PHY + DDRPHY_DTPR2_OFFSET, 0x10029600);
+	write32_x(DDR_PHY + DDRPHY_DTPR2_OFFSET, 0x10029600);
 	/* PTR0 : PHY Timing Params 0
 	 * 5:0 tDLLRST Def 27
 	 * 17:6 tDLLLOCK Def 2750
 	 * 21:18 tITMSRST Def 8
 	 * 31:22 Reserved 0
 	 */
-	write32(DDR_PHY + DDRPHY_PTR0_OFFSET, 0x0022AF9B);
+	write32_x(DDR_PHY + DDRPHY_PTR0_OFFSET, 0x0022AF9B);
 	/* PTR1 : PHY Timing Params 1
 	 * 18:0 : tDINITO DRAM Init time 500us 200,000 Dec 0x30D40
 	 * 29:19 : tDINIT1 DRAM Init time tRFC + 10ns 68
 	 */
-	write32(DDR_PHY + DDRPHY_PTR1_OFFSET, 0x02230D40);
+	write32_x(DDR_PHY + DDRPHY_PTR1_OFFSET, 0x02230D40);
 	/* DQS gating configuration: passive windowing mode */
 	/*
 	 * PGCR: PHY General cofiguration register
@@ -248,18 +248,18 @@ int init_ddr3(void)
 	 * 30 loopback DQS gating 0
 	 * 31 loopback mode 0
 	 */
-	write32(DDR_PHY + DDRPHY_PGCR_OFFSET, 0x01BC2E02);
+	write32_x(DDR_PHY + DDRPHY_PGCR_OFFSET, 0x01BC2E02);
 
 	/* PGSR : Wait for INIT/DLL/Z Done from Power on Reset */
 	if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x00000007))
 		return DDR_TIMEOUT;
 	/* PIR : PHY controlled init */
-	write32(DDR_PHY + DDRPHY_PIR_OFFSET, 0x0000001F);
+	write32_x(DDR_PHY + DDRPHY_PIR_OFFSET, 0x0000001F);
 	/* PGSR : Wait for DRAM Init Done */
 	if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x00000007))
 			return DDR_TIMEOUT;
 	/* PIR : controller DRAM initialization */
-	write32(DDR_PHY + DDRPHY_PIR_OFFSET, 0x00040001);
+	write32_x(DDR_PHY + DDRPHY_PIR_OFFSET, 0x00040001);
 	/* PGSR : Wait for DRAM Init Done */
 	if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x0000000F))
 			return DDR_TIMEOUT;
@@ -269,7 +269,7 @@ int init_ddr3(void)
 						0x00000001))
 		return DDR_TIMEOUT;
 	/* POWCTL : Start the memory Power Up seq*/
-	write32(DDR_PCTL + DDR_PCTL_POWCTL_OFFSET, 0x80000001);
+	write32_x(DDR_PCTL + DDR_PCTL_POWCTL_OFFSET, 0x80000001);
 	/* POWSTAT : wait for POWER_UP_DONE */
 	if (wait_for_completion(DDR_PCTL + DDR_PCTL_POWSTAT_OFFSET,
 						0x00000001))
@@ -282,79 +282,79 @@ int init_ddr3(void)
 	 * 30:19 Reserved 0
 	 * 31 Update 1
 	 */
-	write32(DDR_PCTL + DDR_PCTL_TREFI_OFFSET, 0x8000004E);
+	write32_x(DDR_PCTL + DDR_PCTL_TREFI_OFFSET, 0x8000004E);
 	/* TMRD : t_mrd Timing Register -- Range 2 to 4*/
-	write32(DDR_PCTL + DDR_PCTL_TMRD_OFFSET, 0x00000004);
+	write32_x(DDR_PCTL + DDR_PCTL_TMRD_OFFSET, 0x00000004);
 	/*
 	 * TRFC : t_rfc Timing Register -- Range 15 to 131
 	 * 195ns / 2.5ns 78 x4E
 	 */
-	write32(DDR_PCTL + DDR_PCTL_TRFC_OFFSET, 0x0000004E);
+	write32_x(DDR_PCTL + DDR_PCTL_TRFC_OFFSET, 0x0000004E);
 	/* TRP : t_rp Timing Register -- Range 3 to 7
 	 * 4:0 tRP 12.5 / 2.5 = 5 6 For Now 6-6-6
 	 * 17:16 rpea_extra DDR3 - value 0
 	 */
-	write32(DDR_PCTL + DDR_PCTL_TRP_OFFSET, 0x00000006);
+	write32_x(DDR_PCTL + DDR_PCTL_TRP_OFFSET, 0x00000006);
 	/* TAL : Additive Latency Register -- AL in MR1 */
-	write32(DDR_PCTL + DDR_PCTL_TAL_OFFSET, 0x00000000);
+	write32_x(DDR_PCTL + DDR_PCTL_TAL_OFFSET, 0x00000000);
 	/* TCL : CAS Latency Timing Register -- CASL in MR0 6-6-6 */
-	write32(DDR_PCTL + DDR_PCTL_TCL_OFFSET, 0x00000006);
+	write32_x(DDR_PCTL + DDR_PCTL_TCL_OFFSET, 0x00000006);
 	/* TCWL : CAS Write Latency Register   --CASL-1 */
-	write32(DDR_PCTL + DDR_PCTL_TCWL_OFFSET, 0x00000005);
+	write32_x(DDR_PCTL + DDR_PCTL_TCWL_OFFSET, 0x00000005);
 	/* TRAS : Activate to Precharge cmd time  15 45ns / 2.5ns = 18d */
-	write32(DDR_PCTL + DDR_PCTL_TRAS_OFFSET, 0x0000000F);
+	write32_x(DDR_PCTL + DDR_PCTL_TRAS_OFFSET, 0x0000000F);
 	/* TRC : Min. ROW cycle time  21
 	 * 57.5ns / 2.5ns = 23d Playing safe 24
 	 */
-	write32(DDR_PCTL + DDR_PCTL_TRC_OFFSET, 0x00000015);
+	write32_x(DDR_PCTL + DDR_PCTL_TRC_OFFSET, 0x00000015);
 	/* TRCD : Row to Column Delay  # Range 3 to 7 (TCL = TRCD)
 	 * 12.5ns / 2.5ns = 5 but running 6-6-6  6
 	 */
-	write32(DDR_PCTL + DDR_PCTL_TRCD_OFFSET, 0x00000006);
+	write32_x(DDR_PCTL + DDR_PCTL_TRCD_OFFSET, 0x00000006);
 	/* TRRD : Row to Row delay     -- Range 2 to 6
 	 * 2K Page 10ns / 2.5ns = 4
 	 */
-	write32(DDR_PCTL + DDR_PCTL_TRRD_OFFSET, 0x00000004);
+	write32_x(DDR_PCTL + DDR_PCTL_TRRD_OFFSET, 0x00000004);
 	/* TRTP : Read to Precharge time -- Range 2 to 4
 	 * Largest 4 or 7.5ns / 2.5ns = 4
 	 */
-	write32(DDR_PCTL + DDR_PCTL_TRTP_OFFSET, 0x00000004);
+	write32_x(DDR_PCTL + DDR_PCTL_TRTP_OFFSET, 0x00000004);
 	/* TWR : Write recovery time   -- WR in MR0: 15ns / 2.5ns = 6 */
-	write32(DDR_PCTL + DDR_PCTL_TWR_OFFSET, 0x00000006);
+	write32_x(DDR_PCTL + DDR_PCTL_TWR_OFFSET, 0x00000006);
 	/* TWTR : Write to read turn around time  -- Range 2 to 4
 	 * Largest 4 or 7.5ns / 2.5ns = 4
 	 */
-	write32(DDR_PCTL + DDR_PCTL_TWTR_OFFSET, 0x00000004);
+	write32_x(DDR_PCTL + DDR_PCTL_TWTR_OFFSET, 0x00000004);
 	/* TEXSR : Exit Self Refresh to first valid cmd: tXS 512 */
-	write32(DDR_PCTL + DDR_PCTL_TEXSR_OFFSET, 0x00000200);
+	write32_x(DDR_PCTL + DDR_PCTL_TEXSR_OFFSET, 0x00000200);
 	/* TXP : Exit Power Down to first valid cmd
 	 * tXP 2, Settingto 3 to match PHY
 	 */
-	write32(DDR_PCTL + DDR_PCTL_TXP_OFFSET, 0x00000003);
+	write32_x(DDR_PCTL + DDR_PCTL_TXP_OFFSET, 0x00000003);
 	/* TDQS : t_dqs Timing Register
 	 * DQS additional turn around Rank 2 Rank (1 Rank) Def 1
 	 */
-	write32(DDR_PCTL + DDR_PCTL_TDQS_OFFSET, 0x00000001);
+	write32_x(DDR_PCTL + DDR_PCTL_TDQS_OFFSET, 0x00000001);
 	/* TRTW : Read to Write turn around time Def 3
 	 * Actual gap t_bl + t_rtw
 	 */
-	write32(DDR_PCTL + DDR_PCTL_TRTW_OFFSET, 0x00000003);
+	write32_x(DDR_PCTL + DDR_PCTL_TRTW_OFFSET, 0x00000003);
 	/* TCKE : CKE min pulse width DEf 3 */
-	write32(DDR_PCTL + DDR_PCTL_TCKE_OFFSET, 0x00000003);
+	write32_x(DDR_PCTL + DDR_PCTL_TCKE_OFFSET, 0x00000003);
 	/* TXPDLL : Slow Exit Power Down to first valid cmd delay
 	 * tXARDS 10+AL = 10
 	 */
-	write32(DDR_PCTL + DDR_PCTL_TXPDLL_OFFSET, 0x0000000A);
+	write32_x(DDR_PCTL + DDR_PCTL_TXPDLL_OFFSET, 0x0000000A);
 	/* TCKESR : Min CKE Low width for Self refresh entry to exit
 	 * t_ckesr = 0 DDR2
 	 */
-	write32(DDR_PCTL + DDR_PCTL_TCKESR_OFFSET, 0x00000004);
+	write32_x(DDR_PCTL + DDR_PCTL_TCKESR_OFFSET, 0x00000004);
 	/* TMOD : MRS to any Non-MRS command -- Range 0 to 31 */
-	write32(DDR_PCTL + DDR_PCTL_TMOD_OFFSET, 0x0000000F);
+	write32_x(DDR_PCTL + DDR_PCTL_TMOD_OFFSET, 0x0000000F);
 	/* TZQCS : SDRAM ZQ Calibration Short Period */
-	write32(DDR_PCTL + DDR_PCTL_TZQCS_OFFSET, 0x00000040);
+	write32_x(DDR_PCTL + DDR_PCTL_TZQCS_OFFSET, 0x00000040);
 	/* TZQCL : SDRAM ZQ Calibration Long Period */
-	write32(DDR_PCTL + DDR_PCTL_TZQCL_OFFSET, 0x00000200);
+	write32_x(DDR_PCTL + DDR_PCTL_TZQCL_OFFSET, 0x00000200);
 	/* SCFG : State Configuration Register  (Enabling Self Refresh)
 	 * 0    LP_en Leave Off for Bring Up   0
 	 * 5:1  Reserved
@@ -364,40 +364,40 @@ int init_ddr3(void)
 	 * 16:12 Additional delay on accertion of ac_pdd 4
 	 * 31:17 Reserved
 	 */
-	write32(DDR_PCTL + DDR_PCTL_SCFG_OFFSET, 0x00004480);
+	write32_x(DDR_PCTL + DDR_PCTL_SCFG_OFFSET, 0x00004480);
 	/* TREFI_MEM_DDR3 */
-	write32(DDR_PCTL + DDR_PCTL_TREFI_MEM_DDR3_OFFSET, 0x00000C30);
+	write32_x(DDR_PCTL + DDR_PCTL_TREFI_MEM_DDR3_OFFSET, 0x00000C30);
 
 	/* DFITPHYWRLAT : Write cmd to dfi_wrdata_en */
-	write32(DDR_PCTL + DDR_PCTL_DFIWRLAT_OFFSET, 0x00000002);
+	write32_x(DDR_PCTL + DDR_PCTL_DFIWRLAT_OFFSET, 0x00000002);
 	/* DFITRDDATAEN : Read cmd to dfi_rddata_en */
-	write32(DDR_PCTL + DDR_PCTL_DFITRDDATAEN_OFFSET, 0x00000002);
+	write32_x(DDR_PCTL + DDR_PCTL_DFITRDDATAEN_OFFSET, 0x00000002);
 	/*
 	 * DFITPHYWRDATA : dfi_wrdata_en to drive wr data
 	 * DFI Clks wrdata_en to wrdata Def 1
 	 */
-	write32(DDR_PCTL + DDR_PCTL_DFITPHYWRDATA_OFFSET, 0x00000000);
+	write32_x(DDR_PCTL + DDR_PCTL_DFITPHYWRDATA_OFFSET, 0x00000000);
 	/*
 	 * DFITPHYRDLAT : dfi_rddata_en to dfi_rddata_valid
 	 * DFI clks max rddata_en to rddata_valid Def 15
 	 */
-	write32(DDR_PCTL + DDR_PCTL_DFITPHYRDLAT_OFFSET, 0x00000008);
+	write32_x(DDR_PCTL + DDR_PCTL_DFITPHYRDLAT_OFFSET, 0x00000008);
 	/* DFISTCFG0 : Drive various DFI signals appropriately
 	 * 0 dfi_init_start            1
 	 * 1 dfi_freq_ratio_en         1
 	 * 2 dfi_data_byte_disable_en  1
 	 */
-	write32(DDR_PCTL + DDR_PCTL_DFISTCFG0_OFFSET, 0x00000007);
+	write32_x(DDR_PCTL + DDR_PCTL_DFISTCFG0_OFFSET, 0x00000007);
 	/* DFISTCFG1 : Enable various DFI support
 	 * 0 dfi_dram_clk_disable_en 1
 	 * 1 dfi_dram_clk_disable_en_pdp only lPDDR 0
 	 */
-	write32(DDR_PCTL + DDR_PCTL_DFISTCFG1_OFFSET, 0x00000001);
+	write32_x(DDR_PCTL + DDR_PCTL_DFISTCFG1_OFFSET, 0x00000001);
 	/* DFISTCFG2 : Enable Parity and asoc interrupt
 	 * 0 dfi_parity_in Enable 1
 	 * 1 Interrupt on dfi_parity_error 1
 	 */
-	write32(DDR_PCTL + DDR_PCTL_DFISTCFG2_OFFSET, 0x00000003);
+	write32_x(DDR_PCTL + DDR_PCTL_DFISTCFG2_OFFSET, 0x00000003);
 	/* DFILPCFG0 : DFI Low Power Interface Configuration
 	 * 0     Enable DFI LP IF during PD 1
 	 * 3:1   Reserved
@@ -411,7 +411,7 @@ int init_ddr3(void)
 	 * 27:25 Reserved
 	 * 31:28 DFI LP Deep Power Down Value 0
 	 */
-	write32(DDR_PCTL + DDR_PCTL_DFILPCFG0_OFFSET, 0x00070101);
+	write32_x(DDR_PCTL + DDR_PCTL_DFILPCFG0_OFFSET, 0x00070101);
 	/* DFIODTCFG : DFI ODT Configuration
 	 * Only Enabled on Rank0 Writes
 	 * 0 rank0_odt_read_nsel  0
@@ -419,14 +419,14 @@ int init_ddr3(void)
 	 * 2 rank0_odt_write_nsel 0
 	 * 3 rank0_odt_write_sel  1
 	 */
-	write32(DDR_PCTL + DDR_PCTL_DFIODTCFG_OFFSET, 0x00000008);
+	write32_x(DDR_PCTL + DDR_PCTL_DFIODTCFG_OFFSET, 0x00000008);
 	/* DFIODTCFG1 : DFI ODT Configuration
 	 * 4:0   odt_lat_w     0
 	 * 12:8  odt_lat_r     0 Def
 	 * 4:0   odt_len_bl8_w 6 Def
 	 * 12:8  odt_len_bl8_r 6 Def
 	 */
-	write32(DDR_PCTL + DDR_PCTL_DFIODTCFG1_OFFSET, 0x060600000);
+	write32_x(DDR_PCTL + DDR_PCTL_DFIODTCFG1_OFFSET, 0x060600000);
 
 	/* Memory initialization */
 	/* MCMD : PREA, Addr 0 Bank 0 Rank 0 Del 0
@@ -438,37 +438,37 @@ int init_ddr3(void)
 	 * 30:24 Reserved
 	 */
 	/* MCMD: MR2 */
-	write32(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80004403);
+	write32_x(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80004403);
 	/* MRS cmd wait for completion */
 	if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00004403))
 		return DDR_TIMEOUT;
 	/* MCMD: MR3 */
-	write32(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80000003);
+	write32_x(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80000003);
 	/* MRS cmd wait for completion */
 	if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00000003))
 		return DDR_TIMEOUT;
 	/* MCMD: MR1 */
-	write32(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80000043);
+	write32_x(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80000043);
 	/* MRS cmd wait for completion */
 	if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00000043))
 		return DDR_TIMEOUT;
 	/* MCMD: MR0 */
-	write32(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80015203);
+	write32_x(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80015203);
 	/* MRS cmd wait for completion */
 	if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00015203))
 		return DDR_TIMEOUT;
 	/* MCMD: ZQS cmd, long 5 short 4 */
-	write32(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80104005);
+	write32_x(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80104005);
 	/* MRS cmd wait for completion */
 	if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00104005))
 		return DDR_TIMEOUT;
 	/* MCMD: deselect command */
-	write32(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80100000);
+	write32_x(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x80100000);
 	/* MRS cmd wait for completion */
 	if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x00100000))
 		return DDR_TIMEOUT;
 	/* MCMD: deselect command */
-	write32(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x8010000A);
+	write32_x(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x8010000A);
 	/* MRS cmd wait for completion */
 	if (wait_for_completion(DDR_PCTL + DDR_PCTL_MCMD_OFFSET, 0x0010000A))
 		return DDR_TIMEOUT;
@@ -481,31 +481,31 @@ int init_ddr3(void)
 	 * 10:8 Address Map R/B/C = 1
 	 * 31:11 Reserved
 	 */
-	write32(DDR_PCTL + DDR_PCTL_DCFG_OFFSET, 0x00000116);
+	write32_x(DDR_PCTL + DDR_PCTL_DCFG_OFFSET, 0x00000116);
 	/* PCFG_0 : Port 0 AXI config  */
-	write32(DDR_PCTL + DDR_PCTL_PCFG0_OFFSET, 0x000800A0);
+	write32_x(DDR_PCTL + DDR_PCTL_PCFG0_OFFSET, 0x000800A0);
 	/* SCTL : UPCTL switch INIT CONFIG State */
-	write32(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000001);
+	write32_x(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000001);
 	/* STAT : Wait for Switch INIT to Config State */
 	if (wait_for_completion(DDR_PCTL + DDR_PCTL_STAT_OFFSET, 0x00000001))
 		return DDR_TIMEOUT;
 	/* STAT : Wait for Switch INIT to Config State */
-	write32(DDR_PCTL + DDR_PCTL_CMDTSTATEN_OFFSET, 0x00000001);
+	write32_x(DDR_PCTL + DDR_PCTL_CMDTSTATEN_OFFSET, 0x00000001);
 	/* STAT : Wait for Switch INIT to Config State */
 	if (wait_for_completion(DDR_PCTL + DDR_PCTL_CMDTSTAT_OFFSET,
 							0x00000001))
 		return DDR_TIMEOUT;
 	/* Use PHY for DRAM init */
-	write32(DDR_PHY + DDRPHY_PIR_OFFSET, 0x00000181);
+	write32_x(DDR_PHY + DDRPHY_PIR_OFFSET, 0x00000181);
 	/* STAT : Wait for Switch INIT to Config State */
 	if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x00000001F))
 		return DDR_TIMEOUT;
 	/* Disable Impedance Calibration */
-	write32(DDR_PHY + DDRPHY_ZQ0CR0_OFFSET, 0x3000014A);
-	write32(DDR_PHY + DDRPHY_ZQ1CR0_OFFSET, 0x3000014A);
+	write32_x(DDR_PHY + DDRPHY_ZQ0CR0_OFFSET, 0x3000014A);
+	write32_x(DDR_PHY + DDRPHY_ZQ1CR0_OFFSET, 0x3000014A);
 
 	/* SCTL : UPCTL switch Config to ACCESS State */
-	write32(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000002);
+	write32_x(DDR_PCTL + DDR_PCTL_SCTL_OFFSET, 0x00000002);
 	/* STAT : Wait for switch CFG -> GO State */
 	if (wait_for_completion(DDR_PCTL + DDR_PCTL_STAT_OFFSET, 0x3))
 		return DDR_TIMEOUT;
diff --git a/src/soc/imgtec/pistachio/include/soc/cpu.h b/src/soc/imgtec/pistachio/include/soc/cpu.h
index 2ceb624771..c22dceba45 100644
--- a/src/soc/imgtec/pistachio/include/soc/cpu.h
+++ b/src/soc/imgtec/pistachio/include/soc/cpu.h
@@ -28,7 +28,7 @@
  * If we're not working on the FPGA this will be 0
  */
 #define PRIMARY_FPGA_VERSION		0xB8149060
-#define IMG_PLATFORM_ID()		read32(PRIMARY_FPGA_VERSION)
+#define IMG_PLATFORM_ID()		read32_x(PRIMARY_FPGA_VERSION)
 #define IMG_PLATFORM_ID_FPGA		0xD1400003 /* Last FPGA image */
 #define IMG_PLATFORM_ID_SILICON		0
 
diff --git a/src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h b/src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h
index 1026d5bce1..eab5b3a142 100644
--- a/src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h
+++ b/src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h
@@ -132,7 +132,7 @@ static int wait_for_completion(u32 reg, u32 exp_val)
 	struct stopwatch sw;
 
 	stopwatch_init_usecs_expire(&sw, DDR_TIMEOUT_VALUE_US);
-	while (read32(reg) != exp_val) {
+	while (read32_x(reg) != exp_val) {
 		if (stopwatch_expired(&sw))
 			return DDR_TIMEOUT;
 	}
diff --git a/src/soc/imgtec/pistachio/monotonic_timer.c b/src/soc/imgtec/pistachio/monotonic_timer.c
index 6e40a39148..bbcd8a179d 100644
--- a/src/soc/imgtec/pistachio/monotonic_timer.c
+++ b/src/soc/imgtec/pistachio/monotonic_timer.c
@@ -35,7 +35,7 @@ static int get_count_mhz_freq(void)
 			 * frequency of 550 MHz; otherwise, the crystal is
 			 * used with a frequency of 52 MHz
 			 */
-			if (read32(PISTACHIO_CLOCK_SWITCH) &
+			if (read32_x(PISTACHIO_CLOCK_SWITCH) &
 				MIPS_EXTERN_PLL_BYPASS_MASK)
 				/* Half MIPS PLL freq. */
 				count_mhz_freq = 275;
diff --git a/src/soc/imgtec/pistachio/reset.c b/src/soc/imgtec/pistachio/reset.c
index 244070fe52..cc563372b4 100644
--- a/src/soc/imgtec/pistachio/reset.c
+++ b/src/soc/imgtec/pistachio/reset.c
@@ -22,5 +22,5 @@
 void do_board_reset(void)
 {
 	/* Generate system reset */
-	write32(PISTACHIO_WD_ADDR + PISTACHIO_WD_SW_RST_OFFSET, 0x1);
+	write32_x(PISTACHIO_WD_ADDR + PISTACHIO_WD_SW_RST_OFFSET, 0x1);
 }
diff --git a/src/soc/imgtec/pistachio/spi.c b/src/soc/imgtec/pistachio/spi.c
index cd27ce181d..acbbd909bd 100644
--- a/src/soc/imgtec/pistachio/spi.c
+++ b/src/soc/imgtec/pistachio/spi.c
@@ -48,7 +48,7 @@ static int wait_status(u32 reg, u32 shift)
 	struct stopwatch sw;
 
 	stopwatch_init_usecs_expire(&sw, SPI_TIMEOUT_VALUE_US);
-	while (!(read32(reg) & (1 << shift))) {
+	while (!(read32_x(reg) & (1 << shift))) {
 		if (stopwatch_expired(&sw))
 			return -SPIM_TIMEOUT;
 	}
@@ -71,7 +71,7 @@ static int transmitdata(const struct spi_slave *slave, u8 *buffer, u32 size)
 	base = img_slave->base;
 	while (size) {
 		/* Wait until FIFO empty */
-		write32(base + SPFI_INT_CLEAR_REG_OFFSET, SPFI_SDE_MASK);
+		write32_x(base + SPFI_INT_CLEAR_REG_OFFSET, SPFI_SDE_MASK);
 		ret = wait_status(base + SPFI_INT_STATUS_REG_OFFSET,
 					SPFI_SDE_SHIFT);
 		if (ret)
@@ -84,13 +84,13 @@ static int transmitdata(const struct spi_slave *slave, u8 *buffer, u32 size)
 		blocksize = SPIM_MAX_BLOCK_BYTES;
 		while ((size >= sizeof(u32)) && blocksize) {
 			memcpy(&write_data, buffer, sizeof(u32));
-			write32(base + SPFI_SEND_LONG_REG_OFFSET, write_data);
+			write32_x(base + SPFI_SEND_LONG_REG_OFFSET, write_data);
 			buffer += sizeof(u32);
 			size -= sizeof(u32);
 			blocksize -= sizeof(u32);
 		}
 		while (size && blocksize) {
-			write32(base + SPFI_SEND_BYTE_REG_OFFSET, *buffer);
+			write32_x(base + SPFI_SEND_BYTE_REG_OFFSET, *buffer);
 			buffer++;
 			size--;
 			blocksize--;
@@ -111,35 +111,35 @@ static int receivedata(const struct spi_slave *slave, u8 *buffer, u32 size)
 	 * Do 32bit reads first. Clear status GDEX32BIT here so that the first
 	 * status reg. read gets the actual bit state
 	 */
-	write32(base + SPFI_INT_CLEAR_REG_OFFSET, SPFI_GDEX32BIT_MASK);
+	write32_x(base + SPFI_INT_CLEAR_REG_OFFSET, SPFI_GDEX32BIT_MASK);
 	while (size >= sizeof(u32)) {
 		ret = wait_status(base + SPFI_INT_STATUS_REG_OFFSET,
 					SPFI_GDEX32BIT_SHIFT);
 		if (ret)
 			return ret;
-		read_data = read32(base + SPFI_GET_LONG_REG_OFFSET);
+		read_data = read32_x(base + SPFI_GET_LONG_REG_OFFSET);
 		memcpy(buffer, &read_data, sizeof(u32));
 		buffer += sizeof(u32);
 		size -= sizeof(u32);
 		/* Clear interrupt status on GDEX32BITL */
-		write32(base + SPFI_INT_CLEAR_REG_OFFSET, SPFI_GDEX32BIT_MASK);
+		write32_x(base + SPFI_INT_CLEAR_REG_OFFSET, SPFI_GDEX32BIT_MASK);
 	}
 
 	/*
 	 * Do the remaining 8bit reads. Clear status GDEX8BIT here so that
 	 * the first status reg. read gets the actual bit state
 	 */
-	write32(base + SPFI_INT_CLEAR_REG_OFFSET, SPFI_GDEX8BIT_MASK);
+	write32_x(base + SPFI_INT_CLEAR_REG_OFFSET, SPFI_GDEX8BIT_MASK);
 	while (size) {
 		ret = wait_status(base + SPFI_INT_STATUS_REG_OFFSET,
 					SPFI_GDEX8BIT_SHIFT);
 		if (ret)
 			return ret;
-		*buffer = read32(base + SPFI_GET_BYTE_REG_OFFSET);
+		*buffer = read32_x(base + SPFI_GET_BYTE_REG_OFFSET);
 		buffer++;
 		size--;
 		/* Clear interrupt status on SPFI_GDEX8BIT */
-		write32(base + SPFI_INT_CLEAR_REG_OFFSET, SPFI_GDEX8BIT_MASK);
+		write32_x(base + SPFI_INT_CLEAR_REG_OFFSET, SPFI_GDEX8BIT_MASK);
 	}
 	return SPIM_OK;
 }
@@ -153,7 +153,7 @@ static void  setparams(const struct spi_slave *slave, u32 port,
 
 	base = img_slave->base;
 	spim_parameters = 0;
-	port_state = read32(base + SPFI_PORT_STATE_REG_OFFSET);
+	port_state = read32_x(base + SPFI_PORT_STATE_REG_OFFSET);
 	port_state &= ~((SPIM_PORT0_MASK>>port)|SPFI_PORT_SELECT_MASK);
 	port_state |= params->cs_idle_level<<(SPIM_CS0_IDLE_SHIFT-port);
 	port_state |=
@@ -175,7 +175,7 @@ static void  setparams(const struct spi_slave *slave, u32 port,
 		break;
 	}
 	/* Set port state register */
-	write32(base + SPFI_PORT_STATE_REG_OFFSET, port_state);
+	write32_x(base + SPFI_PORT_STATE_REG_OFFSET, port_state);
 
 	/* Set up values to be written to device parameter register */
 	spim_parameters |= params->bitrate << SPIM_CLK_DIVIDE_SHIFT;
@@ -183,7 +183,7 @@ static void  setparams(const struct spi_slave *slave, u32 port,
 	spim_parameters |= params->cs_hold << SPIM_CS_HOLD_SHIFT;
 	spim_parameters |= params->cs_delay << SPIM_CS_DELAY_SHIFT;
 
-	write32(base + SPFI_PORT_0_PARAM_REG_OFFSET + 4 * port,
+	write32_x(base + SPFI_PORT_0_PARAM_REG_OFFSET + 4 * port,
 			spim_parameters);
 }
 
@@ -349,20 +349,20 @@ static int spim_io(const struct spi_slave *slave, struct spim_buffer *first,
 	 * Soft reset peripheral internals, this will terminate any
 	 * pending transactions
 	 */
-	write32(base + SPFI_CONTROL_REG_OFFSET, SPIM_SOFT_RESET_MASK);
-	write32(base + SPFI_CONTROL_REG_OFFSET, 0);
+	write32_x(base + SPFI_CONTROL_REG_OFFSET, SPIM_SOFT_RESET_MASK);
+	write32_x(base + SPFI_CONTROL_REG_OFFSET, 0);
 	/* Port state register */
-	reg = read32(base +  SPFI_PORT_STATE_REG_OFFSET);
+	reg = read32_x(base +  SPFI_PORT_STATE_REG_OFFSET);
 	reg = spi_write_reg_field(reg, SPFI_PORT_SELECT, slave->cs);
-	write32(base + SPFI_PORT_STATE_REG_OFFSET, reg);
+	write32_x(base + SPFI_PORT_STATE_REG_OFFSET, reg);
 	/* Set transaction register */
 	reg = transaction_reg_setup(first, second);
-	write32(base + SPFI_TRANSACTION_REG_OFFSET, reg);
+	write32_x(base + SPFI_TRANSACTION_REG_OFFSET, reg);
 	/* Clear status */
-	write32(base + SPFI_INT_CLEAR_REG_OFFSET, 0xffffffff);
+	write32_x(base + SPFI_INT_CLEAR_REG_OFFSET, 0xffffffff);
 	/* Set control register */
 	reg = control_reg_setup(first, second);
-	write32(base + SPFI_CONTROL_REG_OFFSET, reg);
+	write32_x(base + SPFI_CONTROL_REG_OFFSET, reg);
 	/* First transaction always exists */
 	transaction[0] = first;
 	trans_count = 1;
@@ -405,8 +405,8 @@ static int spim_io(const struct spi_slave *slave, struct spim_buffer *first,
 	 * Soft reset peripheral internals, this will terminate any
 	 * pending transactions
 	 */
-	write32(base + SPFI_CONTROL_REG_OFFSET, SPIM_SOFT_RESET_MASK);
-	write32(base + SPFI_CONTROL_REG_OFFSET, 0);
+	write32_x(base + SPFI_CONTROL_REG_OFFSET, SPIM_SOFT_RESET_MASK);
+	write32_x(base + SPFI_CONTROL_REG_OFFSET, 0);
 
 	return SPIM_OK;
 }
@@ -435,9 +435,9 @@ static int spi_ctrlr_claim_bus(const struct spi_slave *slave)
 	/* Set device parameters */
 	setparams(slave, slave->cs, &(img_slave->device_parameters));
 	/* Soft reset peripheral internals */
-	write32(img_slave->base + SPFI_CONTROL_REG_OFFSET,
+	write32_x(img_slave->base + SPFI_CONTROL_REG_OFFSET,
 		SPIM_SOFT_RESET_MASK);
-	write32(img_slave->base + SPFI_CONTROL_REG_OFFSET, 0);
+	write32_x(img_slave->base + SPFI_CONTROL_REG_OFFSET, 0);
 	img_slave->initialised = IMG_TRUE;
 	return SPIM_OK;
 }
@@ -455,9 +455,9 @@ static void spi_ctrlr_release_bus(const struct spi_slave *slave)
 	img_slave = get_img_slave(slave);
 	img_slave->initialised = IMG_FALSE;
 	/* Soft reset peripheral internals */
-	write32(img_slave->base + SPFI_CONTROL_REG_OFFSET,
+	write32_x(img_slave->base + SPFI_CONTROL_REG_OFFSET,
 		SPIM_SOFT_RESET_MASK);
-	write32(img_slave->base + SPFI_CONTROL_REG_OFFSET, 0);
+	write32_x(img_slave->base + SPFI_CONTROL_REG_OFFSET, 0);
 }
 
 /* SPI transfer */
diff --git a/src/soc/imgtec/pistachio/uart.c b/src/soc/imgtec/pistachio/uart.c
index a8ef3fa568..a39f2ec4d8 100644
--- a/src/soc/imgtec/pistachio/uart.c
+++ b/src/soc/imgtec/pistachio/uart.c
@@ -36,12 +36,12 @@
 #define GEN_ACCESSOR(name, idx)						\
 static inline uint8_t read_##name(unsigned base_port)			\
 {									\
-	return read8(base_port + (idx << UART_SHIFT));			\
+	return read8((void *)(base_port + (idx << UART_SHIFT)));	\
 }									\
 									\
 static inline void write_##name(unsigned base_port, uint8_t val)	\
 {									\
-	write8(base_port + (idx << UART_SHIFT), val);			\
+	write8((void *)(base_port + (idx << UART_SHIFT)), val);		\
 }
 
 GEN_ACCESSOR(rbr, UART8250_RBR)