soc/mediatek: Add function to raise the CPU frequency of MT8192

Rename all mt_pll_raise_ca53_freq() into mt_pll_raise_little_cpu_freq().
Implement mt_pll_raise_little_cpu_freq() in MT8192.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: I97d9a61f39f2eb27f0c6f911a9199bf0eaae4fbe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

5 files changed, 29 insertions, 3 deletions

diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h
index a1bd96d4aa..0f8732fb6e 100644
--- a/src/soc/mediatek/common/include/soc/pll_common.h
+++ b/src/soc/mediatek/common/include/soc/pll_common.h
@@ -58,6 +58,6 @@ void pll_set_pcw_change(const struct pll *pll);
 void mux_set_sel(const struct mux *mux, u32 sel);
 int pll_set_rate(const struct pll *pll, u32 rate);
 void mt_pll_init(void);
-void mt_pll_raise_ca53_freq(u32 freq);
+void mt_pll_raise_little_cpu_freq(u32 freq);
 
 #endif
diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c
index 0fe94cf0c3..7133fde400 100644
--- a/src/soc/mediatek/mt8173/pll.c
+++ b/src/soc/mediatek/mt8173/pll.c
@@ -417,7 +417,7 @@ void mt_pll_set_aud_div(u32 rate)
 	}
 }
 
-void mt_pll_raise_ca53_freq(u32 freq)
+void mt_pll_raise_little_cpu_freq(u32 freq)
 {
 	pll_set_rate(&plls[APMIXED_ARMCA7PLL], freq); /* freq in Hz */
 }
diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c
index 4570269421..0e96f4cc68 100644
--- a/src/soc/mediatek/mt8183/pll.c
+++ b/src/soc/mediatek/mt8183/pll.c
@@ -362,7 +362,7 @@ void mt_pll_init(void)
 	setbits32(&mt8183_infracfg->module_sw_cg_2_clr, 1 << 4);
 }
 
-void mt_pll_raise_ca53_freq(u32 freq)
+void mt_pll_raise_little_cpu_freq(u32 freq)
 {
 	/* enable [4] intermediate clock armpll_divider_pll1_ck */
 	setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4);
diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h
index 442aa30877..43c2528994 100644
--- a/src/soc/mediatek/mt8192/include/soc/pll.h
+++ b/src/soc/mediatek/mt8192/include/soc/pll.h
@@ -249,6 +249,7 @@ enum {
 
 	MCU_MUX_MASK = 0x3 << 9,
 	MCU_MUX_SRC_PLL = 0x1 << 9,
+	MCU_MUX_SRC_DIV_PLL1 = 0x2 << 9,
 };
 
 enum {
diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c
index 40d92fdc63..e8849df0b0 100644
--- a/src/soc/mediatek/mt8192/pll.c
+++ b/src/soc/mediatek/mt8192/pll.c
@@ -434,3 +434,28 @@ void mt_pll_init(void)
 	/* enable [14] dramc_pll104m_ck */
 	setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14);
 }
+
+void mt_pll_raise_little_cpu_freq(u32 freq)
+{
+	/* enable [4] intermediate clock armpll_divider_pll1_ck */
+	setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4);
+
+	/* switch ca55 clock source to intermediate clock */
+	clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_DIV_PLL1);
+
+	/* disable armpll_ll frequency output */
+	clrbits32(plls[APMIXED_ARMPLL_LL].reg, PLL_EN);
+
+	/* raise armpll_ll frequency */
+	pll_set_rate(&plls[APMIXED_ARMPLL_LL], freq);
+
+	/* enable armpll_ll frequency output */
+	setbits32(plls[APMIXED_ARMPLL_LL].reg, PLL_EN);
+	udelay(PLL_EN_DELAY);
+
+	/* switch ca55 clock source back to armpll_ll */
+	clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
+
+	/* disable [4] intermediate clock armpll_divider_pll1_ck */
+	clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4);
+}