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authorMichael Niewöhner <foss@mniewoehner.de>2020-11-23 22:05:36 +0100
committerMichael Niewöhner <foss@mniewoehner.de>2020-12-04 00:10:38 +0000
commit51f5ff6d27ccb9d4f7e5401fe1c093b173711bf9 (patch)
treefd4934d7a2d0d5de594ee1e9f08d7d6e6fe1a393 /src/soc
parent14512f9a9be08d945830ddb6d0e48f4d6fc1635c (diff)
soc/intel/{skl,cnl}: add NMI_{EN,STS} registers
Add NMI_EN and NMI_STS registers, so they can be configured for using NMI gpios. References: - CMP-LP: Intel doc# 615146-1.2 - CMP-H: Intel doc# 620855-002 - SPT-H: Intel doc# 332691-003 - SPT-LP: Intel doc# 334659-005 - CNP-H: Intel doc# 337868-002 Test: trigger NMI via gpio on Supermicro X11SSM-F did not work before but now makes the Linux kernel complain about a NMI. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I4d57ae89423bdaacf84f0bb0282bbb1c9df94598 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48091 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/cannonlake/gpio.c10
-rw-r--r--src/soc/intel/cannonlake/gpio_cnp_h.c10
-rw-r--r--src/soc/intel/cannonlake/include/soc/gpio_defs.h2
-rw-r--r--src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h2
-rw-r--r--src/soc/intel/skylake/gpio.c8
-rw-r--r--src/soc/intel/skylake/include/soc/gpio_defs.h2
6 files changed, 34 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c
index 3c70ad9a5b..90efacc3f3 100644
--- a/src/soc/intel/cannonlake/gpio.c
+++ b/src/soc/intel/cannonlake/gpio.c
@@ -76,6 +76,8 @@ static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = {
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
+ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPP_ABG",
.acpi_path = "\\_SB.PCI0.GPIO",
@@ -96,6 +98,8 @@ static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = {
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
+ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPP_DFH",
.acpi_path = "\\_SB.PCI0.GPIO",
@@ -116,6 +120,8 @@ static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = {
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
+ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPD",
.acpi_path = "\\_SB.PCI0.GPIO",
@@ -136,6 +142,8 @@ static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = {
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
+ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GP_AC",
.acpi_path = "\\_SB.PCI0.GPIO",
@@ -156,6 +164,8 @@ static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = {
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
+ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPP_CEJ",
.acpi_path = "\\_SB.PCI0.GPIO",
diff --git a/src/soc/intel/cannonlake/gpio_cnp_h.c b/src/soc/intel/cannonlake/gpio_cnp_h.c
index 06e344d16f..a9035ed10f 100644
--- a/src/soc/intel/cannonlake/gpio_cnp_h.c
+++ b/src/soc/intel/cannonlake/gpio_cnp_h.c
@@ -78,6 +78,8 @@ static const struct pad_community cnl_communities[] = {
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
+ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPP_AB",
.acpi_path = "\\_SB.PCI0.GPIO",
@@ -98,6 +100,8 @@ static const struct pad_community cnl_communities[] = {
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
+ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPP_CDG",
.acpi_path = "\\_SB.PCI0.GPIO",
@@ -118,6 +122,8 @@ static const struct pad_community cnl_communities[] = {
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
+ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPD",
.acpi_path = "\\_SB.PCI0.GPIO",
@@ -138,6 +144,8 @@ static const struct pad_community cnl_communities[] = {
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
+ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPP_KHEF",
.acpi_path = "\\_SB.PCI0.GPIO",
@@ -158,6 +166,8 @@ static const struct pad_community cnl_communities[] = {
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
+ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPP_IJ",
.acpi_path = "\\_SB.PCI0.GPIO",
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h
index e7769b5f31..c96a67d69d 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio_defs.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h
@@ -236,6 +236,8 @@
#define GPI_INT_EN_0 0x120
#define GPI_SMI_STS_0 0x180
#define GPI_SMI_EN_0 0x1A0
+#define GPI_NMI_STS_0 0x1c0
+#define GPI_NMI_EN_0 0x1e0
#define PAD_CFG_BASE 0x600
#endif
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h
index bd68b04f9b..4f87459cc4 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h
@@ -310,6 +310,8 @@
#define GPI_INT_EN_0 0x120
#define GPI_SMI_STS_0 0x180
#define GPI_SMI_EN_0 0x1A0
+#define GPI_NMI_STS_0 0x1c0
+#define GPI_NMI_EN_0 0x1e0
#define PAD_CFG_BASE 0x600
#endif
diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c
index 5519762e34..1ac99121fc 100644
--- a/src/soc/intel/skylake/gpio.c
+++ b/src/soc/intel/skylake/gpio.c
@@ -62,6 +62,8 @@ static const struct pad_community skl_gpio_communities[] = {
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
+ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPIO_COM0",
.acpi_path = "\\_SB.PCI0.GPIO",
@@ -84,6 +86,8 @@ static const struct pad_community skl_gpio_communities[] = {
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
+ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPIO_COM1",
.acpi_path = "\\_SB.PCI0.GPIO",
@@ -107,6 +111,8 @@ static const struct pad_community skl_gpio_communities[] = {
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
+ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPIO_COM3",
.acpi_path = "\\_SB.PCI0.GPIO",
@@ -125,6 +131,8 @@ static const struct pad_community skl_gpio_communities[] = {
.gpi_int_en_reg_0 = GPI_INT_EN_0,
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
+ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPIO_COM2",
.acpi_path = "\\_SB.PCI0.GPIO",
diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h
index 2a5e788ef5..de14bb6de9 100644
--- a/src/soc/intel/skylake/include/soc/gpio_defs.h
+++ b/src/soc/intel/skylake/include/soc/gpio_defs.h
@@ -216,5 +216,7 @@
#define GPI_INT_EN_0 0x120
#define GPI_SMI_STS_0 0x180
#define GPI_SMI_EN_0 0x1a0
+#define GPI_NMI_STS_0 0x1c0
+#define GPI_NMI_EN_0 0x1e0
#endif /* _SOC_GPIO_DEFS_H_ */