qcs405: Add UART support

Add support for UART driver in coreboot.

TEST=build & run

Change-Id: Id9626c68eadead8b8ec5ffbc08cab7b0ec36478f
Signed-off-by: Prudhvi Yarlagadda<pyarlaga@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29964
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

7 files changed, 941 insertions, 0 deletions

diff --git a/src/soc/qualcomm/qcs405/Kconfig b/src/soc/qualcomm/qcs405/Kconfig
index 3e8c1ba5be..6bbdd3bf34 100644
--- a/src/soc/qualcomm/qcs405/Kconfig
+++ b/src/soc/qualcomm/qcs405/Kconfig
@@ -11,6 +11,7 @@ config SOC_QUALCOMM_QCS405
 	select GENERIC_UDELAY
 	select HAVE_MONOTONIC_TIMER
 	select ARM64_USE_ARCH_TIMER
+	select HAVE_UART_SPECIAL
 
 if SOC_QUALCOMM_QCS405
 
diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc
index 4df5246e3c..c64e5bcf58 100644
--- a/src/soc/qualcomm/qcs405/Makefile.inc
+++ b/src/soc/qualcomm/qcs405/Makefile.inc
@@ -8,12 +8,14 @@ bootblock-y += spi.c
 bootblock-y += mmu.c
 bootblock-y += gpio.c
 bootblock-y += clock.c
+bootblock-$(CONFIG_DRIVERS_UART) += uart.c
 
 ################################################################################
 verstage-y += timer.c
 verstage-y += spi.c
 verstage-y += gpio.c
 verstage-y += clock.c
+verstage-$(CONFIG_DRIVERS_UART) += uart.c
 
 ################################################################################
 romstage-y += timer.c
@@ -22,6 +24,7 @@ romstage-y += cbmem.c
 romstage-y += gpio.c
 romstage-y += clock.c
 romstage-y += usb.c
+romstage-$(CONFIG_DRIVERS_UART) += uart.c
 
 ################################################################################
 ramstage-y += soc.c
@@ -31,6 +34,7 @@ ramstage-y += cbmem.c
 ramstage-y += gpio.c
 ramstage-y += clock.c
 ramstage-y += usb.c
+ramstage-$(CONFIG_DRIVERS_UART) += uart.c
 
 ################################################################################
 
diff --git a/src/soc/qualcomm/qcs405/include/soc/blsp.h b/src/soc/qualcomm/qcs405/include/soc/blsp.h
new file mode 100644
index 0000000000..6e55d7dd37
--- /dev/null
+++ b/src/soc/qualcomm/qcs405/include/soc/blsp.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2011-2019 The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef __BLSP_H_
+#define __BLSP_H_
+
+typedef enum {
+	BLSP_QUP_ID_0,
+	BLSP_QUP_ID_1,
+	BLSP_QUP_ID_2,
+	BLSP_QUP_ID_3,
+} blsp_qup_id_t;
+
+typedef enum {
+	BLSP_SUCCESS = 0,
+	BLSP_ID_ERROR,
+	BLSP_ERROR,
+	BLSP_UNSUPPORTED
+} blsp_return_t;
+
+typedef enum {
+	BLSP_PROTO_I2C_UIM = 1,
+	BLSP_PROTO_I2C_ONLY,
+	BLSP_PROTO_SPI_ONLY,
+	BLSP_PROTO_UART_FLOW_CTL,
+	BLSP_PROTO_UIM,
+	BLSP_PROTO_I2C_UART,
+} blsp_protocol_t;
+
+blsp_return_t blsp_i2c_init(blsp_qup_id_t id);
+int blsp_i2c_init_board(blsp_qup_id_t id);
+
+#endif
diff --git a/src/soc/qualcomm/qcs405/include/soc/cdp.h b/src/soc/qualcomm/qcs405/include/soc/cdp.h
new file mode 100644
index 0000000000..8e33f4b960
--- /dev/null
+++ b/src/soc/qualcomm/qcs405/include/soc/cdp.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef _QCS405_CDP_H_
+#define _QCS405_CDP_H_
+
+#include <types.h>
+
+unsigned int smem_get_board_machtype(void);
+
+typedef enum {
+	PHY_INTERFACE_MODE_MII,
+	PHY_INTERFACE_MODE_GMII,
+	PHY_INTERFACE_MODE_SGMII,
+	PHY_INTERFACE_MODE_QSGMII,
+	PHY_INTERFACE_MODE_TBI,
+	PHY_INTERFACE_MODE_RMII,
+	PHY_INTERFACE_MODE_RGMII,
+	PHY_INTERFACE_MODE_RGMII_ID,
+	PHY_INTERFACE_MODE_RGMII_RXID,
+	PHY_INTERFACE_MODE_RGMII_TXID,
+	PHY_INTERFACE_MODE_RTBI,
+	PHY_INTERFACE_MODE_XGMII,
+	PHY_INTERFACE_MODE_NONE /* Must be last */
+} phy_interface_t;
+
+typedef struct {
+	gpio_t gpio;
+	unsigned int func;
+	unsigned int dir;
+	unsigned int pull;
+	unsigned int drvstr;
+	unsigned int enable;
+} gpio_func_data_t;
+
+typedef struct {
+	unsigned int m_value;
+	unsigned int n_value;
+	unsigned int d_value;
+} uart_clk_mnd_t;
+
+/* SPI Mode */
+
+typedef enum {
+	NOR_SPI_MODE_0,
+	NOR_SPI_MODE_1,
+	NOR_SPI_MODE_2,
+	NOR_SPI_MODE_3,
+} spi_mode;
+
+/* SPI Chip selects */
+
+typedef enum {
+	SPI_CS_0,
+	SPI_CS_1,
+	SPI_CS_2,
+	SPI_CS_3,
+} spi_cs;
+
+/* Flash Types */
+
+typedef enum {
+	ONLY_NAND,
+	ONLY_NOR,
+	NAND_NOR,
+	NOR_MMC,
+} flash_desc;
+
+#define NO_OF_DBG_UART_GPIOS	2
+
+#define SPI_NOR_FLASH_VENDOR_MICRON       0x1
+#define SPI_NOR_FLASH_VENDOR_SPANSION     0x2
+
+/* SPI parameters */
+
+typedef struct {
+	spi_mode mode;
+	spi_cs chip_select;
+	int vendor;
+} spinorflash_params_t;
+
+typedef struct {
+	unsigned int count;
+	uint8_t addr[7];
+} ipq_gmac_phy_addr_t;
+
+typedef struct {
+	unsigned int base;
+	int unit;
+	unsigned int is_macsec;
+	unsigned int mac_pwr0;
+	unsigned int mac_pwr1;
+	unsigned int mac_conn_to_phy;
+	phy_interface_t phy;
+	ipq_gmac_phy_addr_t phy_addr;
+} ipq_gmac_board_cfg_t;
+
+#define IPQ_GMAC_NMACS		4
+
+enum gale_board_id {
+	BOARD_ID_GALE_PROTO = 0,
+	BOARD_ID_GALE_EVT = 1,
+	BOARD_ID_GALE_EVT2_0 = 2,
+	BOARD_ID_GALE_EVT2_1 = 6,
+	BOARD_ID_GALE_EVT3 = 5,
+};
+
+/* Board specific parameters */
+typedef struct {
+} __packed board_ipq40xx_params_t;
+
+extern board_ipq40xx_params_t *gboard_param;
+
+unsigned int get_board_index(unsigned int machid);
+void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned int count);
+
+#endif
diff --git a/src/soc/qualcomm/qcs405/include/soc/iomap.h b/src/soc/qualcomm/qcs405/include/soc/iomap.h
new file mode 100644
index 0000000000..2ed3e10f76
--- /dev/null
+++ b/src/soc/qualcomm/qcs405/include/soc/iomap.h
@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) 2012 - 2013, 2015, 2019 The Linux Foundation.
+ * All rights reserved.
+ *
+ * Copyright (c) 2008, Google Inc.
+ * All rights reserved.
+ *
+ * Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  * Neither the name of Google, Inc. nor the names of its contributors
+ *    may be used to endorse or promote products derived from this
+ *    software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef __SOC_QUALCOMM_QCS405_IOMAP_H_
+#define __SOC_QUALCOMM_QCS405_IOMAP_H_
+
+#include <device/mmio.h>
+#include <soc/cdp.h>
+#include <soc/blsp.h>
+
+/* Typecast to allow integers being passed as address
+   This needs to be included because vendor code is not compliant with our
+   macros for read/write. Hence, special macros for readl_i and writel_i are
+   included to do this in one place for all occurrences in vendor code
+ */
+#define readl_i(a)           read32((const void *)(a))
+#define writel_i(v, a)       write32((void *)a, v)
+#define clrsetbits_le32_i(addr, clear, set)  \
+	clrsetbits_le32(((void *)(addr)), (clear), (set))
+
+#define GCC_CLK_CTL_REG			((void *)0x01800000u)
+#define MSM_CLK_CTL_BASE		GCC_CLK_CTL_REG
+#define GCC_CLK_BRANCH_ENA		(GCC_CLK_CTL_REG + 0x6000)
+#define		IMEM_AXI		(1 << 17)
+#define		SYS_NOC_APSS_AHB	(1 << 16)
+#define		BIMC_AXI_M0		(1 << 15)
+#define		APSS_AHB		(1 << 14)
+#define		APSS_AXI		(1 << 13)
+#define		MPM_AHB			(1 << 12)
+#define		GMEM_SYS_NOC_AXI	(1 << 11)
+#define		BLSP1_AHB		(1 << 10)
+#define		BLSP1_SLEEP		(1 << 9)
+#define		PRNG_AHB		(1 << 8)
+#define		BOOT_ROM_AHB		(1 << 7)
+#define		MSG_RAM_AHB		(1 << 6)
+#define		TLMM_AHB		(1 << 5)
+#define		TLMM			(1 << 4)
+#define		SPMI_PCNOC_AHB		(1 << 3)
+#define		CRYPTO			(1 << 2)
+#define		CRYPTO_AXI		(1 << 1)
+#define		CRYPTO_AHB		(1 << 0)
+
+#define GCC_BLSP1_QUP1_I2C_APPS_CBCR		(MSM_CLK_CTL_BASE + 0x2008)
+#define GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR	(MSM_CLK_CTL_BASE + 0x200c)
+#define GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR	(MSM_CLK_CTL_BASE + 0x2010)
+#define GCC_BLSP1_QUP2_I2C_APPS_CBCR		(MSM_CLK_CTL_BASE + 0x3010)
+#define GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR	(MSM_CLK_CTL_BASE + 0x3000)
+#define GCC_BLSP1_QUP2_I2C_APPS_CFG_RCGR	(MSM_CLK_CTL_BASE + 0x3004)
+
+#define GCNT_GLOBAL_CTRL_BASE	((void *)0x004a0000u)
+#define GCNT_CNTCR		(GCNT_GLOBAL_CTRL_BASE + 0x1000)
+#define GCNT_GLB_CNTCV_LO	(GCNT_GLOBAL_CTRL_BASE + 0x1008)
+#define GCNT_GLB_CNTCV_HI	(GCNT_GLOBAL_CTRL_BASE + 0x100c)
+#define GCNT_CNTCV_LO		(GCNT_GLOBAL_CTRL_BASE + 0x2000)
+#define GCNT_CNTCV_HI		(GCNT_GLOBAL_CTRL_BASE + 0x2004)
+
+#define GCNT_PSHOLD		((void *)0x004AB000u)
+
+/* RPM interface constants */
+#define RPM_INT           ((void *)0x63020)
+#define RPM_INT_ACK       ((void *)0x63060)
+#define RPM_SIGNAL_COOKIE ((void *)0x47C20)
+#define RPM_SIGNAL_ENTRY  ((void *)0x47C24)
+#define RPM_FW_MAGIC_NUM 0x4D505242
+
+#define TLMM_BASE_ADDR      ((void *)0x01000000)
+#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 * (x))
+#define GPIO_IN_OUT_ADDR(x) (GPIO_CONFIG_ADDR(x) + 4)
+
+/* Yes, this is not a typo... host2 is actually mapped before host1. */
+#define USB_HOST2_XHCI_BASE	0x10000000
+#define USB_HOST2_DWC3_BASE	0x1000C100
+#define USB_HOST2_PHY_BASE	0x100F8800
+#define USB_HOST1_XHCI_BASE	0x11000000
+#define USB_HOST1_DWC3_BASE	0x1100C100
+#define USB_HOST1_PHY_BASE	0x110F8800
+
+#define UART1_DM_BASE		((void *)0x078af000)
+#define UART2_DM_BASE		((void *)0x078B1000)
+
+enum {
+	BLSP1_UART1,
+	BLSP1_UART2,
+};
+
+#define GCC_BLSP1_UART_BCR_BASE		(GCC_CLK_CTL_REG + 0x2038)
+#define GCC_BLSP1_UART_BCR(x)		(GCC_BLSP1_UART_BCR_BASE + (x) * 0xff0)
+#define GCC_BLSP1_UART_APPS_CBCR(x)	(GCC_BLSP1_UART_BCR(x) + 4)
+#define GCC_BLSP1_UART_APPS_CMD_RCGR(x)	(GCC_BLSP1_UART_APPS_CBCR(x) + 8)
+#define GCC_BLSP1_UART_APPS_CFG_RCGR(x)	(GCC_BLSP1_UART_APPS_CMD_RCGR(x) + 4)
+#define GCC_BLSP1_UART_APPS_M(x)	(GCC_BLSP1_UART_APPS_CFG_RCGR(x) + 4)
+#define GCC_BLSP1_UART_APPS_N(x)	(GCC_BLSP1_UART_APPS_M(x) + 4)
+#define GCC_BLSP1_UART_APPS_D(x)	(GCC_BLSP1_UART_APPS_N(x) + 4)
+#define GCC_BLSP1_UART_MISC(x)		(GCC_BLSP1_UART_APPS_D(x) + 4)
+
+#define BLSP1_QUP0_BASE		((void *)0x078B5000)
+#define BLSP1_QUP1_BASE		((void *)0x078B6000)
+#define BLSP1_QUP2_BASE		((void *)0x078B7000)
+#define BLSP1_QUP3_BASE		((void *)0x078B8000)
+
+#define TCSR_BOOT_MISC_DETECT		((void *)0x0193D100)
+#define TCSR_RESET_DEBUG_SW_ENTRY	((void *)0x01940000)
+
+static inline void *blsp_qup_base(blsp_qup_id_t id)
+{
+	switch (id) {
+	case BLSP_QUP_ID_0: return BLSP1_QUP0_BASE;
+	case BLSP_QUP_ID_1: return BLSP1_QUP1_BASE;
+	case BLSP_QUP_ID_2: return BLSP1_QUP2_BASE;
+	case BLSP_QUP_ID_3: return BLSP1_QUP3_BASE;
+	}
+	return NULL;
+}
+
+#define BLSP_MINI_CORE_SHIFT		8
+#define BLSP_MINI_CORE_I2C		(0x2u << BLSP_MINI_CORE_SHIFT)
+#define BLSP_MINI_CORE_MASK		(0xfu << BLSP_MINI_CORE_SHIFT)
+
+#define ETIMEDOUT -10
+#define EINVAL -11
+#define EIO -12
+
+#endif
diff --git a/src/soc/qualcomm/qcs405/include/soc/uart.h b/src/soc/qualcomm/qcs405/include/soc/uart.h
new file mode 100644
index 0000000000..5c8a361c7b
--- /dev/null
+++ b/src/soc/qualcomm/qcs405/include/soc/uart.h
@@ -0,0 +1,273 @@
+/*
+ * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved.*
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __UART_DM_H__
+#define __UART_DM_H__
+
+#define PERIPH_BLK_BLSP 1
+
+#define MSM_BOOT_UART_DM_EXTR_BITS(value, start_pos, end_pos) \
+	((value << (32 - end_pos)) >> (32 - (end_pos - start_pos)))
+
+extern void __udelay(unsigned long usec);
+
+
+enum MSM_BOOT_UART_DM_PARITY_MODE {
+	MSM_BOOT_UART_DM_NO_PARITY,
+	MSM_BOOT_UART_DM_ODD_PARITY,
+	MSM_BOOT_UART_DM_EVEN_PARITY,
+	MSM_BOOT_UART_DM_SPACE_PARITY
+};
+
+/* UART Stop Bit Length */
+enum MSM_BOOT_UART_DM_STOP_BIT_LEN {
+	MSM_BOOT_UART_DM_SBL_9_16,
+	MSM_BOOT_UART_DM_SBL_1,
+	MSM_BOOT_UART_DM_SBL_1_9_16,
+	MSM_BOOT_UART_DM_SBL_2
+};
+
+/* UART Bits per Char */
+enum MSM_BOOT_UART_DM_BITS_PER_CHAR {
+	MSM_BOOT_UART_DM_5_BPS,
+	MSM_BOOT_UART_DM_6_BPS,
+	MSM_BOOT_UART_DM_7_BPS,
+	MSM_BOOT_UART_DM_8_BPS
+};
+
+/* 8-N-1 Configuration */
+#define MSM_BOOT_UART_DM_8_N_1_MODE	(MSM_BOOT_UART_DM_NO_PARITY | \
+					 (MSM_BOOT_UART_DM_SBL_1 << 2) | \
+					 (MSM_BOOT_UART_DM_8_BPS << 4))
+
+/* UART_DM Registers */
+
+/* UART Operational Mode Register */
+#define MSM_BOOT_UART_DM_MR1(base)	((base) + 0x00)
+#define MSM_BOOT_UART_DM_MR2(base)	((base) + 0x04)
+#define MSM_BOOT_UART_DM_RXBRK_ZERO_CHAR_OFF (1 << 8)
+#define MSM_BOOT_UART_DM_LOOPBACK	(1 << 7)
+
+/* UART Clock Selection Register */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_CSR(base)	((base) + 0xA0)
+#else
+#define MSM_BOOT_UART_DM_CSR(base)	((base) + 0x08)
+#endif
+
+/* UART DM TX FIFO Registers - 4 */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_TF(base, x)	((base) + 0x100+(4*(x)))
+#else
+#define MSM_BOOT_UART_DM_TF(base, x)	((base) + 0x70+(4*(x)))
+#endif
+
+/* UART Command Register */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_CR(base)	((base) + 0xA8)
+#else
+#define MSM_BOOT_UART_DM_CR(base)	((base) + 0x10)
+#endif
+#define MSM_BOOT_UART_DM_CR_RX_ENABLE        (1 << 0)
+#define MSM_BOOT_UART_DM_CR_RX_DISABLE       (1 << 1)
+#define MSM_BOOT_UART_DM_CR_TX_ENABLE        (1 << 2)
+#define MSM_BOOT_UART_DM_CR_TX_DISABLE       (1 << 3)
+
+/* UART Channel Command */
+#define MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x)    ((x & 0x0f) << 4)
+#define MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x)    ((x >> 4) << 11)
+#define MSM_BOOT_UART_DM_CR_CH_CMD(x)		\
+	(MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) | MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x))
+#define MSM_BOOT_UART_DM_CMD_NULL            MSM_BOOT_UART_DM_CR_CH_CMD(0)
+#define MSM_BOOT_UART_DM_CMD_RESET_RX        MSM_BOOT_UART_DM_CR_CH_CMD(1)
+#define MSM_BOOT_UART_DM_CMD_RESET_TX        MSM_BOOT_UART_DM_CR_CH_CMD(2)
+#define MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT  MSM_BOOT_UART_DM_CR_CH_CMD(3)
+#define MSM_BOOT_UART_DM_CMD_RES_BRK_CHG_INT MSM_BOOT_UART_DM_CR_CH_CMD(4)
+#define MSM_BOOT_UART_DM_CMD_START_BRK       MSM_BOOT_UART_DM_CR_CH_CMD(5)
+#define MSM_BOOT_UART_DM_CMD_STOP_BRK        MSM_BOOT_UART_DM_CR_CH_CMD(6)
+#define MSM_BOOT_UART_DM_CMD_RES_CTS_N       MSM_BOOT_UART_DM_CR_CH_CMD(7)
+#define MSM_BOOT_UART_DM_CMD_RES_STALE_INT   MSM_BOOT_UART_DM_CR_CH_CMD(8)
+#define MSM_BOOT_UART_DM_CMD_PACKET_MODE     MSM_BOOT_UART_DM_CR_CH_CMD(9)
+#define MSM_BOOT_UART_DM_CMD_MODE_RESET      MSM_BOOT_UART_DM_CR_CH_CMD(C)
+#define MSM_BOOT_UART_DM_CMD_SET_RFR_N       MSM_BOOT_UART_DM_CR_CH_CMD(D)
+#define MSM_BOOT_UART_DM_CMD_RES_RFR_N       MSM_BOOT_UART_DM_CR_CH_CMD(E)
+#define MSM_BOOT_UART_DM_CMD_RES_TX_ERR      MSM_BOOT_UART_DM_CR_CH_CMD(10)
+#define MSM_BOOT_UART_DM_CMD_CLR_TX_DONE     MSM_BOOT_UART_DM_CR_CH_CMD(11)
+#define MSM_BOOT_UART_DM_CMD_RES_BRKSTRT_INT MSM_BOOT_UART_DM_CR_CH_CMD(12)
+#define MSM_BOOT_UART_DM_CMD_RES_BRKEND_INT  MSM_BOOT_UART_DM_CR_CH_CMD(13)
+#define MSM_BOOT_UART_DM_CMD_RES_PER_FRM_INT MSM_BOOT_UART_DM_CR_CH_CMD(14)
+
+/*UART General Command */
+#define MSM_BOOT_UART_DM_CR_GENERAL_CMD(x)   ((x) << 8)
+
+#define MSM_BOOT_UART_DM_GCMD_NULL            MSM_BOOT_UART_DM_CR_GENERAL_CMD(0)
+#define MSM_BOOT_UART_DM_GCMD_CR_PROT_EN      MSM_BOOT_UART_DM_CR_GENERAL_CMD(1)
+#define MSM_BOOT_UART_DM_GCMD_CR_PROT_DIS     MSM_BOOT_UART_DM_CR_GENERAL_CMD(2)
+#define MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT  MSM_BOOT_UART_DM_CR_GENERAL_CMD(3)
+#define MSM_BOOT_UART_DM_GCMD_SW_FORCE_STALE  MSM_BOOT_UART_DM_CR_GENERAL_CMD(4)
+#define MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT   MSM_BOOT_UART_DM_CR_GENERAL_CMD(5)
+#define MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT   MSM_BOOT_UART_DM_CR_GENERAL_CMD(6)
+
+/* UART Interrupt Mask Register */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_IMR(base)             ((base) + 0xB0)
+#else
+#define MSM_BOOT_UART_DM_IMR(base)             ((base) + 0x14)
+#endif
+
+#define MSM_BOOT_UART_DM_TXLEV               (1 << 0)
+#define MSM_BOOT_UART_DM_RXHUNT              (1 << 1)
+#define MSM_BOOT_UART_DM_RXBRK_CHNG          (1 << 2)
+#define MSM_BOOT_UART_DM_RXSTALE             (1 << 3)
+#define MSM_BOOT_UART_DM_RXLEV               (1 << 4)
+#define MSM_BOOT_UART_DM_DELTA_CTS           (1 << 5)
+#define MSM_BOOT_UART_DM_CURRENT_CTS         (1 << 6)
+#define MSM_BOOT_UART_DM_TX_READY            (1 << 7)
+#define MSM_BOOT_UART_DM_TX_ERROR            (1 << 8)
+#define MSM_BOOT_UART_DM_TX_DONE             (1 << 9)
+#define MSM_BOOT_UART_DM_RXBREAK_START       (1 << 10)
+#define MSM_BOOT_UART_DM_RXBREAK_END         (1 << 11)
+#define MSM_BOOT_UART_DM_PAR_FRAME_ERR_IRQ   (1 << 12)
+
+#define MSM_BOOT_UART_DM_IMR_ENABLED         (MSM_BOOT_UART_DM_TX_READY | \
+						MSM_BOOT_UART_DM_TXLEV | \
+						MSM_BOOT_UART_DM_RXSTALE)
+
+/* UART Interrupt Programming Register */
+#define MSM_BOOT_UART_DM_IPR(base)             ((base) + 0x18)
+#define MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB   0x0f
+#define MSM_BOOT_UART_DM_STALE_TIMEOUT_MSB   0	/* Not used currently */
+
+/* UART Transmit/Receive FIFO Watermark Register */
+#define MSM_BOOT_UART_DM_TFWR(base)            ((base) + 0x1C)
+/* Interrupt is generated when FIFO level is less than or equal to this value */
+#define MSM_BOOT_UART_DM_TFW_VALUE           0
+
+#define MSM_BOOT_UART_DM_RFWR(base)            ((base) + 0x20)
+/*Interrupt generated when no of words in RX FIFO is greater than this value */
+#define MSM_BOOT_UART_DM_RFW_VALUE           0
+
+/* UART Hunt Character Register */
+#define MSM_BOOT_UART_DM_HCR(base)             ((base) + 0x24)
+
+/* Used for RX transfer initialization */
+#define MSM_BOOT_UART_DM_DMRX(base)            ((base) + 0x34)
+
+/* Default DMRX value - any value bigger than FIFO size would be fine */
+#define MSM_BOOT_UART_DM_DMRX_DEF_VALUE    0x220
+
+/* Register to enable IRDA function */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_IRDA(base)            ((base) + 0xB8)
+#else
+#define MSM_BOOT_UART_DM_IRDA(base)            ((base) + 0x38)
+#endif
+
+/* UART Data Mover Enable Register */
+#define MSM_BOOT_UART_DM_DMEN(base)            ((base) + 0x3C)
+
+/* Number of characters for Transmission */
+#define MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base) ((base) + 0x040)
+
+/* UART RX FIFO Base Address */
+#define MSM_BOOT_UART_DM_BADR(base)            ((base) + 0x44)
+
+/* UART Status Register */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_SR(base)              ((base) + 0x0A4)
+#else
+#define MSM_BOOT_UART_DM_SR(base)              ((base) + 0x008)
+#endif
+#define MSM_BOOT_UART_DM_SR_RXRDY            (1 << 0)
+#define MSM_BOOT_UART_DM_SR_RXFULL           (1 << 1)
+#define MSM_BOOT_UART_DM_SR_TXRDY            (1 << 2)
+#define MSM_BOOT_UART_DM_SR_TXEMT            (1 << 3)
+#define MSM_BOOT_UART_DM_SR_UART_OVERRUN     (1 << 4)
+#define MSM_BOOT_UART_DM_SR_PAR_FRAME_ERR    (1 << 5)
+#define MSM_BOOT_UART_DM_RX_BREAK            (1 << 6)
+#define MSM_BOOT_UART_DM_HUNT_CHAR           (1 << 7)
+#define MSM_BOOT_UART_DM_RX_BRK_START_LAST   (1 << 8)
+
+/* UART Receive FIFO Registers - 4 in numbers */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_RF(base, x)      ((base) + 0x140 + (4*(x)))
+#else
+#define MSM_BOOT_UART_DM_RF(base, x)      ((base) + 0x70 + (4*(x)))
+#endif
+
+/* UART Masked Interrupt Status Register */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_MISR(base)         ((base) + 0xAC)
+#else
+#define MSM_BOOT_UART_DM_MISR(base)         ((base) + 0x10)
+#endif
+
+/* UART Interrupt Status Register */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_ISR(base)          ((base) + 0xB4)
+#else
+#define MSM_BOOT_UART_DM_ISR(base)          ((base) + 0x14)
+#endif
+
+/* Number of characters received since the end of last RX transfer */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base)  ((base) + 0xBC)
+#else
+#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base)  ((base) + 0x38)
+#endif
+
+/* UART TX FIFO Status Register */
+#define MSM_BOOT_UART_DM_TXFS(base)           ((base) + 0x4C)
+#define MSM_BOOT_UART_DM_TXFS_STATE_LSB(x)   MSM_BOOT_UART_DM_EXTR_BITS(x, 0, 6)
+#define MSM_BOOT_UART_DM_TXFS_STATE_MSB(x)   \
+	MSM_BOOT_UART_DM_EXTR_BITS(x, 14, 31)
+#define MSM_BOOT_UART_DM_TXFS_BUF_STATE(x)   MSM_BOOT_UART_DM_EXTR_BITS(x, 7, 9)
+#define MSM_BOOT_UART_DM_TXFS_ASYNC_STATE(x) \
+	MSM_BOOT_UART_DM_EXTR_BITS(x, 10, 13)
+
+/* UART RX FIFO Status Register */
+#define MSM_BOOT_UART_DM_RXFS(base)           ((base) + 0x50)
+#define MSM_BOOT_UART_DM_RXFS_STATE_LSB(x)   MSM_BOOT_UART_DM_EXTR_BITS(x, 0, 6)
+#define MSM_BOOT_UART_DM_RXFS_STATE_MSB(x)   \
+	MSM_BOOT_UART_DM_EXTR_BITS(x, 14, 31)
+#define MSM_BOOT_UART_DM_RXFS_BUF_STATE(x)   MSM_BOOT_UART_DM_EXTR_BITS(x, 7, 9)
+#define MSM_BOOT_UART_DM_RXFS_ASYNC_STATE(x) \
+	MSM_BOOT_UART_DM_EXTR_BITS(x, 10, 13)
+
+/* Macros for Common Errors */
+#define MSM_BOOT_UART_DM_E_SUCCESS           0
+#define MSM_BOOT_UART_DM_E_FAILURE           1
+#define MSM_BOOT_UART_DM_E_TIMEOUT           2
+#define MSM_BOOT_UART_DM_E_INVAL             3
+#define MSM_BOOT_UART_DM_E_MALLOC_FAIL       4
+#define MSM_BOOT_UART_DM_E_RX_NOT_READY      5
+
+void qcs405_uart_init(void);
+
+#endif				/* __UART_DM_H__ */
diff --git a/src/soc/qualcomm/qcs405/uart.c b/src/soc/qualcomm/qcs405/uart.c
new file mode 100644
index 0000000000..4a4331220a
--- /dev/null
+++ b/src/soc/qualcomm/qcs405/uart.c
@@ -0,0 +1,303 @@
+/*
+ * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved.
+ * Source : APQ8064 LK boot
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <device/mmio.h>
+#include <boot/coreboot_tables.h>
+#include <console/console.h>
+#include <console/uart.h>
+#include <delay.h>
+#include <gpio.h>
+#include <soc/clock.h>
+#include <soc/blsp.h>
+#include <soc/uart.h>
+#include <soc/cdp.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <soc/iomap.h>
+
+#define FIFO_DATA_SIZE	4
+
+typedef struct {
+	void *uart_dm_base;
+	unsigned int blsp_uart;
+	gpio_func_data_t dbg_uart_gpio[NO_OF_DBG_UART_GPIOS];
+} uart_params_t;
+
+void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned int count)
+{
+	int i;
+
+	for (i = 0; i < count; i++) {
+		gpio_configure(gpio->gpio, gpio->func,
+			gpio->pull, gpio->drvstr, gpio->enable);
+		gpio++;
+	}
+}
+
+static const uart_params_t uart_board_param = {
+	.uart_dm_base = UART2_DM_BASE,
+	.blsp_uart = BLSP1_UART2,
+	.dbg_uart_gpio = {
+		{
+			.gpio = GPIO(17),
+			.func = 1,
+			.dir = GPIO_OUTPUT,
+			.pull = GPIO_PULL_UP,
+			.enable = GPIO_OUTPUT
+		},
+		{
+			.gpio = GPIO(18),
+			.func = 1,
+			.dir = GPIO_INPUT,
+			.pull = GPIO_NO_PULL,
+			.enable = GPIO_INPUT
+		},
+	},
+};
+
+/**
+ * @brief msm_boot_uart_dm_init_rx_transfer - Init Rx transfer
+ * @param uart_dm_base: UART controller base address
+ */
+static unsigned int msm_boot_uart_dm_init_rx_transfer(void *uart_dm_base)
+{
+	/* Reset receiver */
+	write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
+		MSM_BOOT_UART_DM_CMD_RESET_RX);
+
+	/* Enable receiver */
+	write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
+		MSM_BOOT_UART_DM_CR_RX_ENABLE);
+	write32(MSM_BOOT_UART_DM_DMRX(uart_dm_base),
+		MSM_BOOT_UART_DM_DMRX_DEF_VALUE);
+
+	/* Clear stale event */
+	write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
+		MSM_BOOT_UART_DM_CMD_RES_STALE_INT);
+
+	/* Enable stale event */
+	write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
+		MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT);
+
+	return MSM_BOOT_UART_DM_E_SUCCESS;
+}
+
+#if CONFIG(DRIVERS_UART)
+static unsigned int msm_boot_uart_dm_init(void  *uart_dm_base);
+
+/* Received data is valid or not */
+static int valid_data = 0;
+
+/* Received data */
+static unsigned int word = 0;
+
+
+void uart_tx_byte(int idx, unsigned char data)
+{
+	int num_of_chars = 1;
+	void *base = uart_board_param.uart_dm_base;
+
+	/* Wait until transmit FIFO is empty. */
+	while (!(read32(MSM_BOOT_UART_DM_SR(base)) &
+		 MSM_BOOT_UART_DM_SR_TXEMT))
+		udelay(1);
+	/*
+	 * TX FIFO is ready to accept new character(s). First write number of
+	 * characters to be transmitted.
+	 */
+	write32(MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base), num_of_chars);
+
+	/* And now write the character(s) */
+	write32(MSM_BOOT_UART_DM_TF(base, 0), data);
+}
+#endif /* CONFIG_SERIAL_UART */
+
+/**
+ * @brief msm_boot_uart_dm_reset - resets UART controller
+ * @param base: UART controller base address
+ */
+static unsigned int msm_boot_uart_dm_reset(void *base)
+{
+	write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RESET_RX);
+	write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RESET_TX);
+	write32(MSM_BOOT_UART_DM_CR(base),
+		MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT);
+	write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RES_TX_ERR);
+	write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RES_STALE_INT);
+
+	return MSM_BOOT_UART_DM_E_SUCCESS;
+}
+
+/**
+ * @brief msm_boot_uart_dm_init - initilaizes UART controller
+ * @param uart_dm_base: UART controller base address
+ */
+unsigned int msm_boot_uart_dm_init(void  *uart_dm_base)
+{
+	/* Configure UART mode registers MR1 and MR2 */
+	/* Hardware flow control isn't supported */
+	write32(MSM_BOOT_UART_DM_MR1(uart_dm_base), 0x0);
+
+	/* 8-N-1 configuration: 8 data bits - No parity - 1 stop bit */
+	write32(MSM_BOOT_UART_DM_MR2(uart_dm_base),
+		MSM_BOOT_UART_DM_8_N_1_MODE);
+
+	/* Configure Interrupt Mask register IMR */
+	write32(MSM_BOOT_UART_DM_IMR(uart_dm_base),
+		MSM_BOOT_UART_DM_IMR_ENABLED);
+
+	/*
+	 * Configure Tx and Rx watermarks configuration registers
+	 * TX watermark value is set to 0 - interrupt is generated when
+	 * FIFO level is less than or equal to 0
+	 */
+	write32(MSM_BOOT_UART_DM_TFWR(uart_dm_base),
+		MSM_BOOT_UART_DM_TFW_VALUE);
+
+	/* RX watermark value */
+	write32(MSM_BOOT_UART_DM_RFWR(uart_dm_base),
+		MSM_BOOT_UART_DM_RFW_VALUE);
+
+	/* Configure Interrupt Programming Register */
+	/* Set initial Stale timeout value */
+	write32(MSM_BOOT_UART_DM_IPR(uart_dm_base),
+		MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB);
+
+	/* Configure IRDA if required */
+	/* Disabling IRDA mode */
+	write32(MSM_BOOT_UART_DM_IRDA(uart_dm_base), 0x0);
+
+	/* Configure hunt character value in HCR register */
+	/* Keep it in reset state */
+	write32(MSM_BOOT_UART_DM_HCR(uart_dm_base), 0x0);
+
+	/*
+	 * Configure Rx FIFO base address
+	 * Both TX/RX shares same SRAM and default is half-n-half.
+	 * Sticking with default value now.
+	 * As such RAM size is (2^RAM_ADDR_WIDTH, 32-bit entries).
+	 * We have found RAM_ADDR_WIDTH = 0x7f
+	 */
+
+	/* Issue soft reset command */
+	msm_boot_uart_dm_reset(uart_dm_base);
+
+	/* Enable/Disable Rx/Tx DM interfaces */
+	/* Data Mover not currently utilized. */
+	write32(MSM_BOOT_UART_DM_DMEN(uart_dm_base), 0x0);
+
+	/* Enable transmitter */
+	write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
+		MSM_BOOT_UART_DM_CR_TX_ENABLE);
+
+	/* Initialize Receive Path */
+	msm_boot_uart_dm_init_rx_transfer(uart_dm_base);
+
+	return 0;
+}
+
+/**
+ * @brief qcs405_uart_init - initializes UART
+ *
+ * Initializes clocks, GPIO and UART controller.
+ */
+void uart_init(int idx)
+{
+	/* Note int idx isn't used in this driver. */
+	void *dm_base;
+
+	dm_base = uart_board_param.uart_dm_base;
+
+	if (read32(MSM_BOOT_UART_DM_CSR(dm_base)) == 0xFF)
+		return; /* UART must have been already initialized. */
+
+	clock_configure_uart(1843200);
+	clock_enable_uart();
+
+	ipq_configure_gpio(uart_board_param.dbg_uart_gpio,
+			   NO_OF_DBG_UART_GPIOS);
+
+	write32(MSM_BOOT_UART_DM_CSR(dm_base), 0xFF);
+
+	/* Initialize UART_DM */
+	msm_boot_uart_dm_init(dm_base);
+}
+
+/* for the benefit of non-console uart init */
+void qcs405_uart_init(void)
+{
+	uart_init(0);
+}
+
+/**
+ * @brief uart_tx_flush - transmits a string of data
+ * @param idx: string to transmit
+ */
+void uart_tx_flush(int idx)
+{
+	void *base = uart_board_param.uart_dm_base;
+
+	while (!(read32(MSM_BOOT_UART_DM_SR(base)) &
+		 MSM_BOOT_UART_DM_SR_TXEMT))
+		;
+}
+
+#if CONFIG(DRIVERS_UART)
+/**
+ * qcs405_serial_getc - reads a character
+ *
+ * Returns the character read from serial port.
+ */
+uint8_t uart_rx_byte(int idx)
+{
+	uint8_t byte;
+
+	byte = (uint8_t)(word & 0xff);
+	word = word >> 8;
+	valid_data--;
+
+	return byte;
+}
+#endif
+
+#ifndef __PRE_RAM__
+void uart_fill_lb(void *data)
+{
+	struct lb_serial serial;
+
+	serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
+	serial.baseaddr = (uint64_t)UART2_DM_BASE;
+	serial.baud = get_uart_baudrate();
+	serial.regwidth = 1;
+
+	lb_add_serial(&serial, data);
+	lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
+}
+#endif