diff options
| author | Julien Viard de Galbert <jviarddegalbert@online.net> | 2018-03-08 16:26:41 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-11-20 00:43:10 +0000 |
| commit | 3065157da825ee2389e05875f78178957ee9dd75 (patch) | |
| tree | 943861988854ec814f881ec17019abf001687059 /src/soc | |
| parent | 69c57e19da3d940b34e8dd3e5ca7eb32e79e391e (diff) | |
soc/intel/denverton_ns: Initialize thermal configuration
Change-Id: I7e1b924154256f8f82ded3d0fa155b3e836d9375
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/denverton_ns/cpu.c | 18 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/include/soc/msr.h | 2 |
2 files changed, 20 insertions, 0 deletions
diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 1fd233a23a..1dc0830d86 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -53,6 +53,21 @@ static void dnv_configure_mca(void) write_cr4(read_cr4() | CR4_MCE); } +static void configure_thermal_core(void) +{ + msr_t msr; + + /* Disable Thermal interrupts */ + msr.lo = 0; + msr.hi = 0; + wrmsr(IA32_THERM_INTERRUPT, msr); + wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); + + msr = rdmsr(IA32_MISC_ENABLE); + msr.lo |= THERMAL_MONITOR_ENABLE_BIT; /* TM1/TM2/EMTTM enable */ + wrmsr(IA32_MISC_ENABLE, msr); +} + static void denverton_core_init(struct device *cpu) { msr_t msr; @@ -62,6 +77,9 @@ static void denverton_core_init(struct device *cpu) /* Clear out pending MCEs */ dnv_configure_mca(); + /* Configure Thermal Sensors */ + configure_thermal_core(); + /* Enable Fast Strings */ msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= FAST_STRINGS_ENABLE_BIT; diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index 1f64235a14..89caf44c17 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -22,6 +22,8 @@ #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) +/* IA32_MISC_ENABLE 0x1a0 */ +#define THERMAL_MONITOR_ENABLE_BIT (1 << 3) #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) #define MSR_TURBO_RATIO_LIMIT 0x1ad |