diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-11-02 16:55:44 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-11-08 19:23:49 +0000 |
| commit | 2d69d75749b7c320fec9c50403add0cea3272687 (patch) | |
| tree | f13fdc9a2c104a8511de736b554394efbab18eab /src/soc | |
| parent | b838256a51b3d58f297165b5d238ea35aba3bce7 (diff) | |
amd/stoneyridge: Add northbridge register macros
Add helpers for determining the D18F1 offset for MMIO base and limit,
and I/O base/limit registers.
Change-Id: I3f61bff00b8f3ada3e1bbfb163e1f223708bd47d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/northbridge.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index 911387836a..0cf94289bb 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -26,15 +26,34 @@ # define CPU_CNT_MASK 0x1f /* CpuCnt + 1 = no. CPUs */ /* D18F1 - Address Map Registers */ + +/* MMIO base and limit */ #define D18F1_MMIO_BASE0_LO 0x80 # define MMIO_WE (1 << 1) # define MMIO_RE (1 << 0) #define D18F1_MMIO_LIMIT0_LO 0x84 # define MMIO_NP (1 << 7) +#define D18F1_MMIO_BASELIM0_HI 0x180 +#define D18F1_MMIO_BASE8_LO 0x1a0 +#define D18F1_MMIO_LIMIT8_LO 0x1a4 +#define D18F1_MMIO_BASELIM8_HI 0x1c0 +#define NB_MMIO_BASE_LO(reg) ((reg) * 2 * sizeof(uint32_t) + (((reg) < 8) \ + ? D18F1_MMIO_BASE0_LO \ + : D18F1_MMIO_BASE8_LO \ + - 8 * sizeof(uint64_t))) +#define NB_MMIO_LIMIT_LO(reg) (NB_MMIO_BASE_LO(reg) + sizeof(uint32_t)) +#define NB_MMIO_BASELIM_HI(reg) ((reg) * sizeof(uint32_t) + (((reg) < 8) \ + ? D18F1_MMIO_BASELIM0_HI \ + : D18F1_MMIO_BASELIM8_HI \ + - 8 * sizeof(uint32_t))) +/* I/O base and limit */ #define D18F1_IO_BASE0 0xc0 # define IO_WE (1 << 1) # define IO_RE (1 << 0) #define D18F1_IO_LIMIT0 0xc4 +#define NB_IO_BASE(reg) ((reg) * 2 * sizeof(uint32_t) + D18F1_IO_BASE0) +#define NB_IO_LIMIT(reg) (NB_IO_BASE(reg) + sizeof(uint32_t)) + #define D18F1_DRAM_HOLE 0xf0 # define DRAM_HOIST_VALID (1 << 1) # define DRAM_HOLE_VALID (1 << 0) |