diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2020-07-28 12:05:17 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-31 09:42:16 +0000 |
| commit | a9eec2cc2f941d6e4035620e60c1a0ae93d5167e (patch) | |
| tree | 02796a15dd2458b8062dfd3ebd1534305e517bb1 /src/soc | |
| parent | 25ec61540885d8e13d654bfbbaeb5123816b665e (diff) | |
soc/intel/cannonlake: Fix DMAR when no iGPU is present
Don't emit RMRR for the iGPU if it's not present. This is done on
other platforms as well.
Fixes an DMAR error seen in dmesg on platforms without iGPU.
Change-Id: Iafe86e6938a120b707aaae935cb8168f790bb22f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43994
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/cannonlake/acpi.c | 19 |
1 files changed, 11 insertions, 8 deletions
diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 3f3ba10024..f061c30bf4 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -285,8 +285,8 @@ static unsigned long soc_fill_dmar(unsigned long current) struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; - - if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten) { + const bool emit_igd = igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten; + if (emit_igd) { unsigned long tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); @@ -326,12 +326,15 @@ static unsigned long soc_fill_dmar(unsigned long current) acpi_dmar_drhd_fixup(tmp, current); } - /* Add RMRR entry */ - const unsigned long tmp = current; - current += acpi_create_dmar_rmrr(current, 0, - sa_get_gsm_base(), sa_get_tolud_base() - 1); - current += acpi_create_dmar_ds_pci(current, 0, 2, 0); - acpi_dmar_rmrr_fixup(tmp, current); + /* Add RMRR entry after all DRHD entries */ + if (emit_igd) { + const unsigned long tmp = current; + + current += acpi_create_dmar_rmrr(current, 0, + sa_get_gsm_base(), sa_get_tolud_base() - 1); + current += acpi_create_dmar_ds_pci(current, 0, 2, 0); + acpi_dmar_rmrr_fixup(tmp, current); + } return current; } |