diff options
| author | Furquan Shaikh <furquan@google.com> | 2016-06-22 14:00:09 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2016-06-23 23:11:35 +0200 |
| commit | a1850bafbffd147bd5aad8b2a6463f40cc28ddec (patch) | |
| tree | a8354f37911c8b257fabe560b7a72c4b8f55ab0f /src/soc | |
| parent | f359997f8632a4a81ee39fc27f79f5e27ab072eb (diff) | |
intel/apollolake: Enable prefetching and caching for BIOS reads
Change-Id: I6afcc17ec8511d3fd4c1ac3b15d523d9b6752120
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15321
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/spi.h | 9 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/spi.c | 5 |
2 files changed, 10 insertions, 4 deletions
diff --git a/src/soc/intel/apollolake/include/soc/spi.h b/src/soc/intel/apollolake/include/soc/spi.h index 20e78d7843..cc508e1b67 100644 --- a/src/soc/intel/apollolake/include/soc/spi.h +++ b/src/soc/intel/apollolake/include/soc/spi.h @@ -19,14 +19,15 @@ /* PCI configuration registers */ #define SPIBAR_BIOS_CONTROL 0xdc +/* Bit definitions for BIOS_CONTROL */ +#define SPIBAR_BIOS_CONTROL_WPD (1 << 0) +#define SPIBAR_BIOS_CONTROL_CACHE_DISABLE (1 << 2) +#define SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE (1 << 3) +#define SPIBAR_BIOS_CONTROL_EISS (1 << 5) /* Maximum bytes of data that can fit in FDATAn registers */ #define SPIBAR_FDATA_FIFO_SIZE 0x40 -/* Bit definitions for BIOS_CONTROL */ -#define SPIBAR_BIOS_CONTROL_WPD (1 << 0) -#define SPIBAR_BIOS_CONTROL_EISS (1 << 5) - /* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */ #define SPIBAR_BIOS_BFPREG 0x00 #define SPIBAR_HSFSTS_CTL 0x04 diff --git a/src/soc/intel/apollolake/spi.c b/src/soc/intel/apollolake/spi.c index 282ed013a6..7b390bb2b9 100644 --- a/src/soc/intel/apollolake/spi.c +++ b/src/soc/intel/apollolake/spi.c @@ -203,6 +203,11 @@ void spi_init(void) bios_ctl = pci_read_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL); bios_ctl |= SPIBAR_BIOS_CONTROL_WPD; bios_ctl &= ~SPIBAR_BIOS_CONTROL_EISS; + + /* Enable Prefetching and caching. */ + bios_ctl |= SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE; + bios_ctl &= ~SPIBAR_BIOS_CONTROL_CACHE_DISABLE; + pci_write_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL, bios_ctl); } |