diff options
| author | Matt DeVillier <matt.devillier@gmail.com> | 2018-03-02 14:22:14 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-03-26 10:21:07 +0000 |
| commit | 6dd4f76c77af8b12a7dc5d617b9c72f63ea1352f (patch) | |
| tree | c59721c42df1e2cc98c367cccfb765194752a5bf /src/soc | |
| parent | ea5c0a15abcc7fda2f95b83a40ab3bd879ae2f0b (diff) | |
soc/skylake/cpu: Fix Intel SpeedStep enable/disable
In an attempt at consolidation, commit 0a203d1 [1] introduced
an additional read/write of the MISC_ENABLE msr, as well a bug
which nullified the setting of Intel SpeedStep by inserting said
read/write calls in between another set of read/write calls to the
same msr. Fix by reverting to previous (simpler) implementation.
[1] soc/intel/skylake: Use CPU common library code
https://review.coreboot.org/19566
Test: boot Linux on Librem13v2, read MISC_ENABLE msr and verify
SpeedStep bit correctly set based on devicetree setting.
Change-Id: Id2ac660bf8ea56d45e8c3f631a586b74106a6cc9
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/25330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/skylake/cpu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 6e98afaffd..1a2de73f8d 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -293,9 +293,9 @@ static void configure_misc(void) msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ if (conf->eist_enable) - cpu_enable_eist(); + msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ else - cpu_disable_eist(); + msr.lo &= ~(1 << 16); /* Enhanced SpeedStep Disable */ wrmsr(IA32_MISC_ENABLE, msr); /* Disable Thermal interrupts */ |