vboot: fix CONFIG_RESUME_PATH_SAME_AS_BOOT S3 resume logic

- should not check VBOOT_STARTS_IN_BOOTBLOCK to set context flag
- implement vboot_platform_is_resuming on platforms missing it
- add ACPI_INTEL_HARDWARE_SLEEP_VALUES to two intel southbridges

[ originally https://review.coreboot.org/c/coreboot/+/28750 ]

BUG=b:114018226
TEST=compile coreboot

Change-Id: I1ef0bcdfd01746198f8140f49698b58065d820b9
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/29060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>

4 files changed, 36 insertions, 0 deletions

diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c
index 51c3ea065b..06751f1a80 100644
--- a/src/soc/intel/baytrail/pmutil.c
+++ b/src/soc/intel/baytrail/pmutil.c
@@ -14,6 +14,7 @@
  */
 
 #include <stdint.h>
+#include <arch/acpi.h>
 #include <arch/io.h>
 #include <cbmem.h>
 #include <console/console.h>
@@ -23,6 +24,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pmc.h>
 #include <security/vboot/vbnv.h>
+#include <security/vboot/vboot_common.h>
 
 #if defined(__SIMPLE_DEVICE__)
 
@@ -384,3 +386,11 @@ int vbnv_cmos_failed(void)
 {
 	return rtc_failure();
 }
+
+int vboot_platform_is_resuming(void)
+{
+	if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS))
+		return 0;
+
+	return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3;
+}
diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c
index 00284d1604..85384a6120 100644
--- a/src/soc/intel/braswell/pmutil.c
+++ b/src/soc/intel/braswell/pmutil.c
@@ -14,6 +14,7 @@
  * GNU General Public License for more details.
  */
 
+#include <arch/acpi.h>
 #include <arch/io.h>
 #include <cbmem.h>
 #include <console/console.h>
@@ -24,6 +25,7 @@
 #include <soc/pm.h>
 #include <stdint.h>
 #include <security/vboot/vbnv.h>
+#include <security/vboot/vboot_common.h>
 
 #if defined(__SIMPLE_DEVICE__)
 
@@ -380,3 +382,11 @@ int vbnv_cmos_failed(void)
 {
 	return rtc_failure();
 }
+
+int vboot_platform_is_resuming(void)
+{
+	if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS))
+		return 0;
+
+	return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3;
+}
diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c
index 38991305b4..e19025bf7a 100644
--- a/src/soc/intel/broadwell/pmutil.c
+++ b/src/soc/intel/broadwell/pmutil.c
@@ -18,6 +18,7 @@
  * and the differences between PCH variants.
  */
 
+#include <arch/acpi.h>
 #include <arch/io.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -29,6 +30,7 @@
 #include <soc/pm.h>
 #include <soc/gpio.h>
 #include <security/vboot/vbnv.h>
+#include <security/vboot/vboot_common.h>
 
 /* Print status bits with descriptive names */
 static void print_status_bits(u32 status, const char *bit_names[])
@@ -473,3 +475,11 @@ int vbnv_cmos_failed(void)
 {
 	return rtc_failure();
 }
+
+int vboot_platform_is_resuming(void)
+{
+	if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS))
+		return 0;
+
+	return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3;
+}
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c
index f8d985eaea..fb5962e59c 100644
--- a/src/soc/intel/fsp_baytrail/romstage/romstage.c
+++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c
@@ -39,6 +39,7 @@
 #include <version.h>
 #include <pc80/mc146818rtc.h>
 #include <device/pci_def.h>
+#include <security/vboot/vboot_common.h>
 
 /* Return 0, 3, 4 or 5 to indicate the previous sleep state. */
 uint32_t chipset_prev_sleep_state(uint32_t clear)
@@ -271,3 +272,8 @@ uint64_t get_initial_timestamp(void)
 {
 	return 0;
 }
+
+int vboot_platform_is_resuming(void)
+{
+	return !!romstage_handoff_is_resume();
+}