diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-02-19 20:48:29 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-24 13:01:15 +0000 |
| commit | 1b296ee3b832bc9dbff57c680a3de509db3c95fd (patch) | |
| tree | e6a93116bfb42b4d60d03da80464ca9614ed8469 /src/soc | |
| parent | e9f86c1016bc71eb0d9f7bb4b5f3ce36c56f100b (diff) | |
soc/{samsung,sifive}: Fix typos
Change-Id: Ib370f04a63160e2a8a1b06620e659feb45c8f552
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/samsung/exynos5420/spi.c | 2 | ||||
| -rw-r--r-- | src/soc/sifive/fu540/clock.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c index a98f51d72c..ec9002399b 100644 --- a/src/soc/samsung/exynos5420/spi.c +++ b/src/soc/samsung/exynos5420/spi.c @@ -101,7 +101,7 @@ static void exynos_spi_init(struct exynos_spi *regs) // CPOL: Active high. clrbits32(®s->ch_cfg, SPI_CH_CPOL_L); - // Clear rx and tx channel if set priveously. + // Clear rx and tx channel if set previously. clrbits32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); setbits32(®s->swap_cfg, diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c index a15e639839..ad5e06b65e 100644 --- a/src/soc/sifive/fu540/clock.c +++ b/src/soc/sifive/fu540/clock.c @@ -104,7 +104,7 @@ static void configure_pll(u32 *reg, const struct pll_settings *s) * Set coreclk according to the SiFive FU540-C000 Manual * https://www.sifive.com/documentation/chips/freedom-u540-c000-manual/ * - * Section 7.1 recommends a frequency of 1.0 GHz (up to 1.5 Ghz is possible) + * Section 7.1 recommends a frequency of 1.0 GHz (up to 1.5 GHz is possible) * * Section 7.4.2 provides the necessary values: * For example, to setup COREPLL for 1 GHz operation, program divr = 0 (x1), |