summaryrefslogtreecommitdiff
path: root/src/soc
diff options
context:
space:
mode:
authorArthur Heymans <arthur.heymans@9elements.com>2021-09-13 09:16:44 +0200
committerLean Sheng Tan <sheng.tan@9elements.com>2024-03-27 09:09:03 +0000
commitfc95c94d810c8dd183142516e30538b4c6a9ff47 (patch)
treef375480b9808aa60f8228d4de998fd94fa76bbab /src/soc
parent44955582a73c1aa69b133fe4d91af5a8fb8b7159 (diff)
soc/intel/xeon_sp/spr: Enable x86_64 support
Fix compilation errors when compiled for x86_64. Test: Booted on ibm/sbp1 to linux payload. Change-Id: I2c5ed0339a9c2e9b088b16dbb4c19df98e796d65 Signed-off-by: Arthur Heymans <arthur.heymans@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81280 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/xeon_sp/spr/Kconfig1
-rw-r--r--src/soc/intel/xeon_sp/spr/romstage.c6
-rw-r--r--src/soc/intel/xeon_sp/spr/upd_display.c4
3 files changed, 6 insertions, 5 deletions
diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
index 3c3c45ace4..23d2f8b6d7 100644
--- a/src/soc/intel/xeon_sp/spr/Kconfig
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
@@ -16,6 +16,7 @@ config SOC_INTEL_SAPPHIRERAPIDS_SP
select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND
select UDK_202005_BINDING
select SOC_INTEL_HAS_CXL
+ select HAVE_EXP_X86_64_SUPPORT
help
Intel Sapphire Rapids-SP support
diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c
index 3b38828492..91d2099632 100644
--- a/src/soc/intel/xeon_sp/spr/romstage.c
+++ b/src/soc/intel/xeon_sp/spr/romstage.c
@@ -114,7 +114,7 @@ static void initialize_iio_upd(FSPM_UPD *mupd)
{
unsigned int port, socket;
- mupd->FspmConfig.IioPcieConfigTablePtr = (UINT32)spr_iio_bifur_table;
+ mupd->FspmConfig.IioPcieConfigTablePtr = (uintptr_t)spr_iio_bifur_table;
/* MAX_SOCKET is the maximal number defined by FSP, currently is 4. */
mupd->FspmConfig.IioPcieConfigTableNumber = MAX_SOCKET;
UPD_IIO_PCIE_PORT_CONFIG *PciePortConfig =
@@ -130,7 +130,7 @@ static void initialize_iio_upd(FSPM_UPD *mupd)
PciePortConfig[socket].PcieMaxReadRequestSize = 0x5;
}
- mupd->FspmConfig.DeEmphasisPtr = (UINT32)deemphasis_list;
+ mupd->FspmConfig.DeEmphasisPtr = (uintptr_t)deemphasis_list;
mupd->FspmConfig.DeEmphasisNumber = MAX_SOCKET * MAX_IIO_PORTS_PER_SOCKET;
UINT8 *DeEmphasisConfig = (UINT8 *)deemphasis_list;
@@ -287,7 +287,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
UPD_IIO_PCIE_PORT_CONFIG *iio_pcie_cfg;
int socket;
- iio_pcie_cfg = (UPD_IIO_PCIE_PORT_CONFIG *)mupd->FspmConfig.IioPcieConfigTablePtr;
+ iio_pcie_cfg = (UPD_IIO_PCIE_PORT_CONFIG *)(uintptr_t)mupd->FspmConfig.IioPcieConfigTablePtr;
for (socket = 0; socket < MAX_SOCKET; socket++)
iio_pcie_cfg[socket].PcieGlobalAspm = 0;
diff --git a/src/soc/intel/xeon_sp/spr/upd_display.c b/src/soc/intel/xeon_sp/spr/upd_display.c
index c69a9a0562..b3c0c7c101 100644
--- a/src/soc/intel/xeon_sp/spr/upd_display.c
+++ b/src/soc/intel/xeon_sp/spr/upd_display.c
@@ -12,7 +12,7 @@ static void soc_display_fspm_upd_iio(const FSPM_UPD *mupd)
int port, socket;
UPD_IIO_PCIE_PORT_CONFIG *PciePortConfig =
- (UPD_IIO_PCIE_PORT_CONFIG *)mupd->FspmConfig.IioPcieConfigTablePtr;
+ (UPD_IIO_PCIE_PORT_CONFIG *)(uintptr_t)mupd->FspmConfig.IioPcieConfigTablePtr;
printk(BIOS_SPEW, "UPD values for IIO:\n");
for (socket = 0; socket < mupd->FspmConfig.IioPcieConfigTableNumber; socket++) {
@@ -94,7 +94,7 @@ static void soc_display_fspm_upd_iio(const FSPM_UPD *mupd)
PciePortConfig[socket].PcieMaxReadRequestSize);
}
- UINT8 *DeEmphasisConfig = (UINT8 *)mupd->FspmConfig.DeEmphasisPtr;
+ UINT8 *DeEmphasisConfig = (UINT8 *)(uintptr_t)mupd->FspmConfig.DeEmphasisPtr;
for (port = 0; port < mupd->FspmConfig.DeEmphasisNumber; port++) {
printk(BIOS_SPEW, "port: %d, DeEmphasisConfig: 0x%x\n", port,
DeEmphasisConfig[port]);