diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2021-03-16 13:23:38 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-03-18 02:33:28 +0000 |
| commit | f2df29e4058d2dda92437f156c0cca6b1c02d389 (patch) | |
| tree | 30a8856057eb27f98878549cd89819ebb442b032 /src/soc | |
| parent | a763e8f92b9faeb70f63304f974551479ac3859b (diff) | |
soc/amd/cezanne/pci_gpp: Add ACPI names for GPP bridges
We are currently writing invalid ACPI tables. We are missing the GPP
ACPI names. There is an assert in acpi_device_write_pci_dev that checks
to see if we have a scope, but by default asserts don't halt, so we were
writing a NULL scope.
BUG=b:171234996
TEST=Boot majolica and dump ACPI tables
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6a861ad1b9259ac3b79af76e18a9354997b0491e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/cezanne/pcie_gpp.c | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/pcie_gpp.c b/src/soc/amd/cezanne/pcie_gpp.c index 0a6bfe26db..4ab206b231 100644 --- a/src/soc/amd/cezanne/pcie_gpp.c +++ b/src/soc/amd/cezanne/pcie_gpp.c @@ -1,9 +1,50 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpi_device.h> +#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pciexp.h> +#include <soc/pci_devs.h> + +static const char *pcie_gpp_acpi_name(const struct device *dev) +{ + if (dev->path.type != DEVICE_PATH_PCI) + return NULL; + + switch (dev->path.pci.devfn) { + case PCIE_GPP_1_0_DEVFN: + return "GP10"; + case PCIE_GPP_1_1_DEVFN: + return "GP11"; + case PCIE_GPP_1_2_DEVFN: + return "GP12"; + case PCIE_GPP_2_0_DEVFN: + return "GP20"; + case PCIE_GPP_2_1_DEVFN: + return "GP21"; + case PCIE_GPP_2_2_DEVFN: + return "GP22"; + case PCIE_GPP_2_3_DEVFN: + return "GP23"; + case PCIE_GPP_2_4_DEVFN: + return "GP24"; + case PCIE_GPP_2_5_DEVFN: + return "GP25"; + case PCIE_GPP_2_6_DEVFN: + return "GP26"; + case PCIE_ABC_A_DEVFN: + return "GPPA"; + case PCIE_GPP_B_DEVFN: + return "GPPB"; + case PCIE_GPP_C_DEVFN: + return "GPPC"; + default: + printk(BIOS_ERR, "%s: Unhanded devfn 0x%x\n", __func__, dev->path.pci.devfn); + return NULL; + } +} static struct device_operations internal_pcie_gpp_ops = { .read_resources = pci_bus_read_resources, @@ -11,6 +52,8 @@ static struct device_operations internal_pcie_gpp_ops = { .enable_resources = pci_bus_enable_resources, .scan_bus = pci_scan_bridge, .reset_bus = pci_bus_reset, + .acpi_name = pcie_gpp_acpi_name, + .acpi_fill_ssdt = acpi_device_write_pci_dev, }; static const struct pci_driver internal_pcie_gpp_driver __pci_driver = { @@ -25,6 +68,8 @@ static struct device_operations external_pcie_gpp_ops = { .enable_resources = pci_bus_enable_resources, .scan_bus = pciexp_scan_bridge, .reset_bus = pci_bus_reset, + .acpi_name = pcie_gpp_acpi_name, + .acpi_fill_ssdt = acpi_device_write_pci_dev, }; static const unsigned short external_pci_gpp_ids[] = { |