diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-11-25 15:41:02 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-11-30 14:39:54 +0000 |
| commit | efe402a3484bcd29cf8d36b770eda4c792fae05c (patch) | |
| tree | a666ae626e8d8fbb922631f570173b27697c66fb /src/soc | |
| parent | 783a8745451bac529c04e4855943bd0faa6be693 (diff) | |
soc/amd/common/block/include/lpc: add missing LPC_PCI_CONTROL bit defs
Both SPI_ROM_BIOS_SEMAPHORE and SPI_ROM_EC_SEMAPHORE bits in the
LPC_PCI_CONTROL are defined in the Stoneyridge BKDG #55072 Rev 3.04,
Raven1 and Picasso PPR #55570 Rev 3.18, Raven2 PPR #55772 Rev 3.08 and
Cezanne PPR #56569 Rev 3.03 which are all platforms that use this code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I855e640d020daf21c9f5b2f62a2ad0fd0274a575
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/lpc.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index c5f3c78821..173cbd15ff 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -10,6 +10,8 @@ #define LEGACY_DMA_EN BIT(2) #define VW_ROM_SHARING_EN BIT(3) #define EXT_ROM_SHARING_EN BIT(4) +#define SPI_ROM_BIOS_SEMAPHORE BIT(5) +#define SPI_ROM_EC_SEMAPHORE BIT(6) #define LPC_IO_PORT_DECODE_ENABLE 0x44 #define DECODE_ENABLE_PARALLEL_PORT0 BIT(0) |