diff options
| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2023-08-25 11:05:02 +0200 |
|---|---|---|
| committer | Michał Żygowski <michal.zygowski@3mdeb.com> | 2023-10-16 08:30:37 +0000 |
| commit | ed4bc980fa6768edf991166582c68f4e3abde8e7 (patch) | |
| tree | 75943922b060212a0817ce8eab57f54fc9fabe89 /src/soc | |
| parent | ed3b688e76b9ec76cfee2dec7f0e3f56ad0e0f41 (diff) | |
soc/intel/common/block/acpi/northbridge.asl: Reserve SBREG BAR
Reserve SBREG BAR if it is outside of the PCH reserved memory range.
Desktop series processors have larger SBREG BARs, which, unlike mobile
processors, do not fall into the standard PCH reserved range
(0xfc800000 - 0xfe7fffff). Create a separate reservation for such a case. There is no telling what could happen if the reservation is not
made in ACPI.
TEST=Boot Windows 11 and Ubuntu 22.04 on MSI PRO Z690-A DDR4
Change-Id: Ibaf45daba37e3acfcea0e653df69fa5c2f480c4a
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77445
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/common/block/acpi/acpi/northbridge.asl | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl index 44c873c8e5..03295b4ca7 100644 --- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <arch/hpet.h> +#include <commonlib/bsd/helpers.h> #include <soc/iomap.h> Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) @@ -165,6 +166,15 @@ Method (_CRS, 0, Serialized) 0x00000000, 0x10000, 0x1ffff, 0x00000000, 0x10000,,, PM02) +#if !((CONFIG_PCR_BASE_ADDRESS >= PCH_PRESERVED_BASE_ADDRESS) && \ + (CONFIG_PCR_BASE_ADDRESS < PCH_PRESERVED_BASE_ADDRESS + PCH_PRESERVED_BASE_SIZE)) + /* SBREG BAR if outside of PCH reserved resource */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x000000000, 0x00000000, 0x00000000, + 0x00000000,,, SM01) +#endif + /* PCH reserved resource (0xfc800000-0xfe7fffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, @@ -192,6 +202,18 @@ Method (_CRS, 0, Serialized) PMIN = \_SB.PCI0.MCHC.TLUD & (0xfff << 20) PLEN = PMAX - PMIN + 1 +#if !((CONFIG_PCR_BASE_ADDRESS >= PCH_PRESERVED_BASE_ADDRESS) && \ + (CONFIG_PCR_BASE_ADDRESS < PCH_PRESERVED_BASE_ADDRESS + PCH_PRESERVED_BASE_SIZE)) + /* Fix up SBREG BAR memory region if outside PCH reserved resource */ + CreateDwordField (MCRS, SM01._MIN, SMIN) + CreateDwordField (MCRS, SM01._MAX, SMAX) + CreateDwordField (MCRS, SM01._LEN, SLEN) + + SMIN = P2SB_BAR + SLEN = P2SB_SIZE + SMAX = SMIN + SLEN - 1 +#endif + /* Patch PM02 range based on Memory Size */ If (A4GS == 0) { CreateQwordField (MCRS, PM02._LEN, MSEN) |