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authorMartin Roth <gaumless@gmail.com>2023-03-20 13:27:34 -0600
committerFred Reitberger <reitbergerfred@gmail.com>2023-03-23 13:05:54 +0000
commite32565cd2d6447ebee9a55580b905026582f9a76 (patch)
tree7f323ac433140ecc6bd2793ab54d8d6b72ff1709 /src/soc
parent14701a4df3cd40fe1eb817e8a1b3bfa064e7f7c1 (diff)
soc/amd/mendocino: Remove GPP bridge to Bus B
The internal GPP bridge to bus B is not used on MDN, so remove it. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4f95afd192c5b799b7a3e12650476b7933cdd118 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/mendocino/chipset_mendocino.cb1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/amd/mendocino/chipset_mendocino.cb b/src/soc/amd/mendocino/chipset_mendocino.cb
index c28c5fc9f6..b4efdf593e 100644
--- a/src/soc/amd/mendocino/chipset_mendocino.cb
+++ b/src/soc/amd/mendocino/chipset_mendocino.cb
@@ -63,7 +63,6 @@ chip soc/amd/mendocino
device pci 0.6 alias hda off end # Audio Processor HD Audio Controller (main AZ)
device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2)
end
- device pci 08.2 alias gpp_bridge_b off ops amd_internal_pcie_gpp_ops end # Internal GPP Bridge 1 to Bus B
device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C
ops amd_internal_pcie_gpp_ops
device pci 0.0 alias xhci_2 off end # Might also be a dummy device with different PCI DID