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authorKrishna Prasad Bhat <krishna.p.bhat.d@intel.com>2022-01-16 21:26:56 +0530
committerSubrata Banik <subratabanik@google.com>2022-02-01 10:13:06 +0000
commite258df2cb7f0522c15b4ba451fda0ce66fb38597 (patch)
tree81e67f2ac38fc52ae2c8f386f219ab3638d98e3f /src/soc
parentb627964f2e08cd93c3a41a8793aef9f215d1c7e3 (diff)
soc/intel/alderlake: Add eMMC PCR Port ID for Alder Lake N
Alder Lake N has eMMC storage device. Add PCR Port ID for it. Reference: Alder Lake N platform EDS Doc# 645548. Change-Id: I6dc494d1748e66b8b4058954f127ec226863e8af Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/alderlake/include/soc/pcr_ids.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/include/soc/pcr_ids.h b/src/soc/intel/alderlake/include/soc/pcr_ids.h
index f125ee20cd..623a8140ba 100644
--- a/src/soc/intel/alderlake/include/soc/pcr_ids.h
+++ b/src/soc/intel/alderlake/include/soc/pcr_ids.h
@@ -33,6 +33,9 @@
#define PID_ITSS 0xc4
#define PID_SERIALIO 0xcb
+/* eMMC Port ID for Alder Lake N */
+#define PID_EMMC 0xa1
+
/* CPU Port IDs */
#define PID_CPU_GPIOCOM0 0xb7
#define PID_CPU_GPIOCOM1 0xb8