diff options
| author | Werner Zeh <werner.zeh@siemens.com> | 2017-01-12 06:29:04 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-01-13 17:42:26 +0100 |
| commit | deed5fbebdb879beccbe2421f1dd3af33301c51a (patch) | |
| tree | bfafb92abb6167380a71b5efe3d302ed165b9627 /src/soc | |
| parent | eec3402339246b98ab35ab880a3f7eac614a8cb5 (diff) | |
fsp_baytrail: Enable graphic init per default
Baytrail SoC has a bug where in some cases the DisplayPort can hang
leading to a non-working display (it just stays black). To avoid this
hang, a patch was introduced in 02/2016
(1c3b1112fa - fsp_baytrail: Fix a possible hanging DisplayPort)
but per default not switched on so that each
mainboard can decide if it wants to use this patch or not.
Recently a new case of this bug was reported by Benoit Sansoni
(benoit.sansoni@kontron.com) and he requested to enable this fix per
default as it costs him a lot of time to find the cause and even the
already available fix in coreboot. To avoid this effort for someone
else in the future we can enable this fix per default as no negative
side effects are known and it is now tested at Siemens and at
Kontron on different mainboards with success.
As the goal is to enable this code permanently the config switch is not
longer needed and is removed.
Change-Id: I15bd682218d0dc887945cc91ee3e5488945a6355
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/18109
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/fsp_baytrail/Kconfig | 8 | ||||
| -rw-r--r-- | src/soc/intel/fsp_baytrail/Makefile.inc | 2 |
2 files changed, 1 insertions, 9 deletions
diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 689e625535..549ea55d19 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -95,14 +95,6 @@ config VGA_BIOS_FILE string default "../intel/cpu/baytrail/vbios/Vga.dat" if VGA_BIOS -config FSP_BAYTRAIL_GFX_INIT - default n - bool - help - Enabling this option will activate graphics init code. With this init, - the graphic power gate registers will be initialized before - VBIOS is executed. - config CPU_MICROCODE_HEADER_FILES string default "../intel/cpu/baytrail/microcode/M0130673322.h ../intel/cpu/baytrail/microcode/M0130679901.h ../intel/cpu/baytrail/microcode/M0230672228.h" diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index 6e16b426a0..f0866652c4 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -57,7 +57,7 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c ramstage-y += placeholders.c ramstage-y += i2c.c -ramstage-$(CONFIG_FSP_BAYTRAIL_GFX_INIT) += gfx.c +ramstage-y += gfx.c CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/include CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp |