soc/intel/broadwell: Use common early SMBus code

Disabling interrupts and clearing errors was being done twice, once in
the `smbus_enable_iobar` reg-script, and another in `enable_smbus`.

Change-Id: I58558996bd693b302764965a5bed8b96db363833
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

3 files changed, 1 insertions, 36 deletions

diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 0ea5dbd065..35129af8b7 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -17,6 +17,7 @@ config CPU_SPECIFIC_OPTIONS
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select HAVE_SMI_HANDLER
+	select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS
 	select SOUTHBRIDGE_INTEL_COMMON_RESET
 	select SOUTHBRIDGE_INTEL_COMMON_RTC
 	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc
index a53cd95cd5..edfec30fdc 100644
--- a/src/soc/intel/broadwell/romstage/Makefile.inc
+++ b/src/soc/intel/broadwell/romstage/Makefile.inc
@@ -5,6 +5,5 @@ romstage-y += power_state.c
 romstage-y += raminit.c
 romstage-y += report_platform.c
 romstage-y += romstage.c
-romstage-y += smbus.c
 romstage-y += systemagent.c
 romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c
diff --git a/src/soc/intel/broadwell/romstage/smbus.c b/src/soc/intel/broadwell/romstage/smbus.c
deleted file mode 100644
index a000255ca9..0000000000
--- a/src/soc/intel/broadwell/romstage/smbus.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/pci_def.h>
-#include <device/smbus_host.h>
-#include <reg_script.h>
-#include <soc/iomap.h>
-#include <soc/pci_devs.h>
-#include <soc/smbus.h>
-#include <soc/romstage.h>
-
-static const struct reg_script smbus_init_script[] = {
-	/* Set SMBUS I/O base address */
-	REG_PCI_WRITE32(SMB_BASE, SMBUS_BASE_ADDRESS | 1),
-	/* Set SMBUS enable */
-	REG_PCI_WRITE8(HOSTC, HST_EN),
-	/* Enable I/O access */
-	REG_PCI_WRITE16(PCI_COMMAND, PCI_COMMAND_IO),
-	/* Disable interrupts */
-	REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTCTL, 0),
-	/* Clear errors */
-	REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTSTAT, 0xff),
-	/* Indicate the end of this array by REG_SCRIPT_END */
-	REG_SCRIPT_END,
-};
-
-uintptr_t smbus_base(void)
-{
-	return SMBUS_BASE_ADDRESS;
-}
-
-int smbus_enable_iobar(uintptr_t base)
-{
-	reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script);
-	return 0;
-}