diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2024-04-04 08:49:19 +0200 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-04-15 08:26:56 +0000 |
| commit | dc735c19c7a1b5cc4e37c7f0c73e13b0072bdd9a (patch) | |
| tree | 11142ec623000ed87baf0f912609a1cfd719035f /src/soc | |
| parent | 0ad214846c384291eabd46176bad7a54c6c11e52 (diff) | |
soc/intel/xeon_sp/spr: Use official microcodes
Use the official microcode updates from intel-microcode submodule
by default. Downstream users can still decide to use their own files.
Change-Id: I58121cc2ca7699d3d26581d7d5875ec74deeeb93
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81637
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/Makefile.mk | 3 |
2 files changed, 3 insertions, 1 deletions
diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index 7887bd01a6..401c8e4981 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -3,7 +3,6 @@ config SOC_INTEL_SAPPHIRERAPIDS_SP bool select FSP_NVS_DATA_POST_SILICON_INIT - select MICROCODE_BLOB_NOT_HOOKED_UP select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select DISABLE_ACPI_HIBERNATE select DEFAULT_X2APIC_RUNTIME diff --git a/src/soc/intel/xeon_sp/spr/Makefile.mk b/src/soc/intel/xeon_sp/spr/Makefile.mk index d288df6fe6..a3d6af5cc2 100644 --- a/src/soc/intel/xeon_sp/spr/Makefile.mk +++ b/src/soc/intel/xeon_sp/spr/Makefile.mk @@ -19,4 +19,7 @@ ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/spr/include -I$(src)/soc/intel/xeon_sp/spr +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8f-08 +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-cf-02 + endif ## CONFIG_SOC_INTEL_SAPPHIRERAPIDS_SP |