diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2024-01-16 00:50:46 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-01-25 22:51:15 +0000 |
| commit | dc12a3817ae49123fadbe99fcab6c039f3b4b53d (patch) | |
| tree | b571b16563f0208c0b2f4bccc669820f98653f98 /src/soc | |
| parent | e5197e17786a5ebf231e1fd93e45b22fb753df6e (diff) | |
soc/amd/genoa_poc: rely less on boot state hooks
Call setup_opensil, opensil_entry, and fch_init in the right order from
the init method of the SoC's chip operations. This brings this SoC both
more in line with the other SoCs and avoids using boot state hooks for
this which also makes the sequence in which those functions are called
easier to understand. Previously the boot states were used so that
setup_opensil was run before configure_mpio which was run before
opensil_entry(SIL_TP1), but since configure_mpio is called from
setup_opensil, this is no longer necessary.
TEST=Onyx still boots to the payload and the MPIO configuration reported
from the openSIL code is still the same. The FCH init code now runs
before the resource allocation like on the AMD SoCs that rely on FSP.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic752635da5eaa9e333cfb927836f0d260d2ac049
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79985
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/genoa_poc/chip.c | 7 | ||||
| -rw-r--r-- | src/soc/amd/genoa_poc/fch.c | 8 | ||||
| -rw-r--r-- | src/soc/amd/genoa_poc/include/soc/southbridge.h | 1 |
3 files changed, 9 insertions, 7 deletions
diff --git a/src/soc/amd/genoa_poc/chip.c b/src/soc/amd/genoa_poc/chip.c index eb35a25bf8..5f29428955 100644 --- a/src/soc/amd/genoa_poc/chip.c +++ b/src/soc/amd/genoa_poc/chip.c @@ -3,10 +3,17 @@ #include <device/device.h> #include <soc/southbridge.h> #include <soc/acpi.h> +#include <soc/southbridge.h> +#include <vendorcode/amd/opensil/genoa_poc/opensil.h> static void soc_init(void *chip_info) { default_dev_ops_root.write_acpi_tables = soc_acpi_write_tables; + + setup_opensil(); + opensil_entry(SIL_TP1); + + fch_init(chip_info); } static void soc_final(void *chip_info) diff --git a/src/soc/amd/genoa_poc/fch.c b/src/soc/amd/genoa_poc/fch.c index c9779571da..f340d82c39 100644 --- a/src/soc/amd/genoa_poc/fch.c +++ b/src/soc/amd/genoa_poc/fch.c @@ -81,14 +81,8 @@ static void fch_init_acpi_ports(void) configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI); } -static void fch_init(void *unused) +void fch_init(void *chip_info) { set_pci_irqs(); fch_init_acpi_ports(); } - -/* - * Hook this function into the PCI state machine on entry into BS_DEV_ENABLE. - * TODO: can this be done without using BOOT_STATE_INIT_ENTRY? - */ -BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fch_init, NULL); diff --git a/src/soc/amd/genoa_poc/include/soc/southbridge.h b/src/soc/amd/genoa_poc/include/soc/southbridge.h index a761d533c3..1027a58455 100644 --- a/src/soc/amd/genoa_poc/include/soc/southbridge.h +++ b/src/soc/amd/genoa_poc/include/soc/southbridge.h @@ -117,5 +117,6 @@ void fch_pre_init(void); void fch_early_init(void); +void fch_init(void *chip_info); #endif /* AMD_GENOA_POC_SOUTHBRIDGE_H */ |