diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-11-24 15:42:35 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-11-26 08:41:49 +0000 |
| commit | da527ec12b01d4794c2b99576dc49bfedadac767 (patch) | |
| tree | 8559edca0e9b6ea25171e477bc8469c751d086d7 /src/soc | |
| parent | 11433c8e98e0fc274f993b54cb2644c47c9739b3 (diff) | |
soc/intel/cmn/cse: Create API to get CSE Lite WP Information
This patch creates an API for CSE-Lite specific SKU to retrieve the
Write Protect (WP) information (`cse_log_ro_write_protection_info`)
like WP range and limit, if the region is write-protected or not etc.
BUG=none
TEST=Able to compile the cse_lite.c file for google/kano without
any error.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8f4b7880534ded5401b6f8d601ded88019c636c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69968
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/common/block/cse/cse_lite.c | 23 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/cse.h | 3 |
2 files changed, 26 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index f051061e7d..37640f43f6 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -10,6 +10,7 @@ #include <intelbasecode/debug_feature.h> #include <intelblocks/cse.h> #include <intelblocks/cse_layout.h> +#include <intelblocks/spi.h> #include <security/vboot/misc.h> #include <security/vboot/vboot_common.h> #include <soc/intel/common/reset.h> @@ -133,6 +134,28 @@ struct get_bp_info_rsp { static const char * const cse_regions[] = {"RO", "RW"}; +void cse_log_ro_write_protection_info(bool mfg_mode) +{ + bool cse_ro_wp_en = is_spi_wp_cse_ro_en(); + + printk(BIOS_DEBUG, "ME: WP for RO is enabled : %s\n", + cse_ro_wp_en ? "YES" : "NO"); + + if (cse_ro_wp_en) { + uint32_t base, limit; + spi_get_wp_cse_ro_range(&base, &limit); + printk(BIOS_DEBUG, "ME: RO write protection scope - Start=0x%X, End=0x%X\n", + base, limit); + } + + /* + * If manufacturing mode is disabled, but CSE RO is not write protected, + * log error. + */ + if (!mfg_mode && !cse_ro_wp_en) + printk(BIOS_ERR, "ME: Write protection for CSE RO is not enabled\n"); +} + bool cse_get_boot_performance_data(struct cse_boot_perf_rsp *boot_perf_rsp) { struct cse_boot_perf_req { diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index f7aae1c0cd..cceee4f8ac 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -555,4 +555,7 @@ void soc_disable_heci1_using_pcr(void); */ void cse_get_telemetry_data(void); +/* Function to log the cse WP information like range, if WP etc. */ +void cse_log_ro_write_protection_info(bool mfg_mode); + #endif // SOC_INTEL_COMMON_CSE_H |