diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-07-12 23:46:21 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-07-14 02:19:51 +0000 |
| commit | ceb2fbb9203c66478f1566d7fcfebc5d807bdb32 (patch) | |
| tree | 8137e9eb19d88e682a8d59ab5640c60f48861a14 /src/soc | |
| parent | 78ab06ace918f6efa1a36c896b85806c5f617393 (diff) | |
include/cpu/x86/msr: add IA32_ prefix to MC0_ADDR and MC0_MISC
Those registers are architectural MSR and this also gets them in line
with IA32_MC0_CTL and IA32_MC0_STATUS. Also move them below the
definitions for IA32_MC0_STATUS, so that the numbers of the MSRs are
ascending.
Change-Id: Icef6526c896720248f5b648ddf1a271bdf46917c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56235
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/stoneyridge/mca.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index 1523563d0c..c2ec402bd3 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -169,10 +169,10 @@ void check_mca(void) printk(BIOS_WARNING, " MC%d_STATUS = %08x_%08x\n", i, mci.sts.hi, mci.sts.lo); - mci.addr = rdmsr(MC0_ADDR + (i * 4)); + mci.addr = rdmsr(IA32_MC0_ADDR + (i * 4)); printk(BIOS_WARNING, " MC%d_ADDR = %08x_%08x\n", i, mci.addr.hi, mci.addr.lo); - mci.misc = rdmsr(MC0_MISC + (i * 4)); + mci.misc = rdmsr(IA32_MC0_MISC + (i * 4)); printk(BIOS_WARNING, " MC%d_MISC = %08x_%08x\n", i, mci.misc.hi, mci.misc.lo); mci.ctl = rdmsr(IA32_MC0_CTL + (i * 4)); |