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authorKyösti Mälkki <kyosti.malkki@gmail.com>2018-06-25 18:53:36 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2018-06-27 10:24:46 +0000
commitce9f422b512c376ba0eeec41db92d9a87155105a (patch)
tree3646411b80f3413804e211fd0c2a61c9e33cdd3c /src/soc
parentc3bc6cbe9de9d65d25009fec8ae5475371724c6e (diff)
x86/car: Replace reference of copy_and_run location
For cases with POSTCAR_STAGE=y this reference pulled in the implementation of run_ramstage() which we would not call. Using _program results with the same region being marked as WRPROT-cacheble. Change-Id: Ie1eaf6f5bb8baa13e946112c4fc3d854dbf750a3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/27232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Keith Hui <buurin@gmail.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/broadwell/romstage/cache_as_ram.inc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
index d1bb3eef48..fd9f829286 100644
--- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc
+++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
@@ -136,7 +136,7 @@ clear_mtrrs:
* IMPORTANT: The following calculation _must_ be done at runtime. See
* https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
- movl $copy_and_run, %eax
+ movl $_program, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRPROT, %eax
wrmsr