diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-03-03 22:37:34 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-06 17:20:45 +0000 |
| commit | cbe55a1728e4f5f3c46e92754fb098aab85fbe91 (patch) | |
| tree | 2b5abe4eaaf5735291f78d49273180e672087c15 /src/soc | |
| parent | c8755141c0849fad536ec12451230f0fd4a6a62a (diff) | |
soc/amd: rename ACPI_CPU_CONTROL to ACPI_CSTATE_CONTROL for non-CAR CPUs
The legacy ACPI CPU control registers in IO space where the first 4 IO
locations control the CPU throttling value don't exist any more on the
Zen-based CPUs. Instead this IO address is written to MSR_CSTATE_ADDRESS
in set_cstate_io_addr which will cause accesses from the 8 IO addresses
beginning with ACPI_CSTATE_CONTROL to be trapped in the CPU core. Reads
from those IO addresses will cause the CPU to enter low C states.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2c34e201cc0add1026edd7a97c70aa57f057782b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/iomap.h | 2 | ||||
| -rw-r--r-- | src/soc/amd/common/block/cpu/noncar/cpu.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/glinda/include/soc/iomap.h | 2 | ||||
| -rw-r--r-- | src/soc/amd/mendocino/include/soc/iomap.h | 2 | ||||
| -rw-r--r-- | src/soc/amd/phoenix/include/soc/iomap.h | 2 | ||||
| -rw-r--r-- | src/soc/amd/picasso/include/soc/iomap.h | 4 |
6 files changed, 7 insertions, 7 deletions
diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h index fc04b256a8..e4fe00fb1b 100644 --- a/src/soc/amd/cezanne/include/soc/iomap.h +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -42,7 +42,7 @@ #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) #define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) #define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08) -#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10) +#define ACPI_CSTATE_CONTROL (ACPI_IO_BASE + 0x10) #define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) diff --git a/src/soc/amd/common/block/cpu/noncar/cpu.c b/src/soc/amd/common/block/cpu/noncar/cpu.c index 8fd371564e..8151b964d0 100644 --- a/src/soc/amd/common/block/cpu/noncar/cpu.c +++ b/src/soc/amd/common/block/cpu/noncar/cpu.c @@ -24,6 +24,6 @@ void set_cstate_io_addr(void) msr_t cst_addr; cst_addr.hi = 0; - cst_addr.lo = ACPI_CPU_CONTROL; + cst_addr.lo = ACPI_CSTATE_CONTROL; wrmsr(MSR_CSTATE_ADDRESS, cst_addr); } diff --git a/src/soc/amd/glinda/include/soc/iomap.h b/src/soc/amd/glinda/include/soc/iomap.h index bb8588ce3c..b335b3fda1 100644 --- a/src/soc/amd/glinda/include/soc/iomap.h +++ b/src/soc/amd/glinda/include/soc/iomap.h @@ -50,7 +50,7 @@ #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) #define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) #define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08) -#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10) +#define ACPI_CSTATE_CONTROL (ACPI_IO_BASE + 0x10) #define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) diff --git a/src/soc/amd/mendocino/include/soc/iomap.h b/src/soc/amd/mendocino/include/soc/iomap.h index 630940bb3f..1e1120cfbe 100644 --- a/src/soc/amd/mendocino/include/soc/iomap.h +++ b/src/soc/amd/mendocino/include/soc/iomap.h @@ -48,7 +48,7 @@ #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) #define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) #define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08) -#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10) +#define ACPI_CSTATE_CONTROL (ACPI_IO_BASE + 0x10) #define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) diff --git a/src/soc/amd/phoenix/include/soc/iomap.h b/src/soc/amd/phoenix/include/soc/iomap.h index 5a1488b343..b12b48c0b6 100644 --- a/src/soc/amd/phoenix/include/soc/iomap.h +++ b/src/soc/amd/phoenix/include/soc/iomap.h @@ -48,7 +48,7 @@ #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) #define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) #define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08) -#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10) +#define ACPI_CSTATE_CONTROL (ACPI_IO_BASE + 0x10) #define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index c70c64ec42..26022ef032 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -69,8 +69,8 @@ #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */ #define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) /* 2 bytes */ #define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08) /* 4 bytes */ -#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10) /* 8 bytes */ -/* doc says 0x14 for GPE0_BLK but 8 bytes from ACPI_CPU_CONTROL on are trapped in CPU core */ +#define ACPI_CSTATE_CONTROL (ACPI_IO_BASE + 0x10) /* 8 bytes */ +/* doc says 0x14 for GPE0_BLK but 8 bytes from ACPI_CSTATE_CONTROL on are trapped in CPU core */ #define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) /* 8 bytes */ #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */ #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) /* 4 bytes */ |