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authorSubrata Banik <subrata.banik@intel.com>2021-06-21 19:07:48 +0530
committerSubrata Banik <subrata.banik@intel.com>2021-06-23 08:25:37 +0000
commitc3a5c0558d39da153f291267f76bb4693ea0955d (patch)
tree4d302fb88506f7a0eada47ddfa27d7a582ea4e11 /src/soc
parent1a5d4120e63015b4e6024f37f77c0c8af2177a65 (diff)
soc/intel/tigerlake: Use devfn_disable() function for XDCI
Use devfn_disable() for disabling a PCI device rather than using `dev->enabled = 0`. Also, use is_devfn_enabled() to get the device current state prior updating the FSP-S UPD for XDCI. TEST=FSP-S disabled XDCI when `xdci_can_enable` returns 0 and XDCI is disabled at PCI enumeration `PCI: 00:14.1: enabled 0`. Change-Id: I0e400ded7ba268a5f289b0ac568598e0dad1899a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55722 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/tigerlake/fsp_params.c11
1 files changed, 3 insertions, 8 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 823f8e543c..7efcfab2da 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -258,14 +258,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
}
/* Enable xDCI controller if enabled in devicetree and allowed */
- dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
- if (dev) {
- if (!xdci_can_enable())
- dev->enabled = 0;
- params->XdciEnable = dev->enabled;
- } else {
- params->XdciEnable = 0;
- }
+ if (!xdci_can_enable())
+ devfn_disable(pci_root_bus(), PCH_DEVFN_USBOTG);
+ params->XdciEnable = is_devfn_enabled(PCH_DEVFN_USBOTG);
/* PCH UART selection for FSP Debug */
params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;