soc/intel/cmn/cse: Create another config for sending CSE EOP cmd late

Presently, coreboot supports two instances of sending EOP cmd to
the Intel CSE.

1. Sending EOP cmd to CSE during `.final` operation from cse pci driver.
2. Starting with Alder Lake, the recommendation was to send EOP to CSE
earlier than CSE `.final` operation. Since then it's referred to as
`Sending EOP Early`. This method helped to save the CSE EOP
response time significantly.

During Meteor Lake platform, CSE EOP response time has become
non-deterministic and we have figured that sending EOP command later
than CSE .final operation is actually helping to optimize the boot time
significantly (around ~150ms savings compared to sending from `.final`
ops and ~5sec compared to sending CSE early).

Hence, this patch intended to create yet another kconfig for sending
CSE late (specifically after `.final` operation). The idea for this
newer config is to use the boot state machine for sending CSE EOP cmd.

The patch train in this series would add the specific changes to allow
sending EOP late and perform other essential operations required prior
booting to OS as coreboot decided to skip calling into FSP Notify phase.

Starting with Jasper Lake, coreboot sends EOP before loading payload
hence, this config is applicable for those platforms.

The current plan is that Intel Jasper Lake, Tiger Lake and Meteor Lake
platform will select this newer config from SoC code.

BUG=b:260041679
TEST=Able to send EOP command successfully for Google/Taeko.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iea512cd5b79d61dd5d5a962079baf525027c831f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69976
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 15 insertions, 0 deletions

diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig
index 55a2b49194..2962a1472e 100644
--- a/src/soc/intel/common/block/cse/Kconfig
+++ b/src/soc/intel/common/block/cse/Kconfig
@@ -54,6 +54,19 @@ config SOC_INTEL_CSE_SEND_EOP_EARLY
 	  In later stages, CSE might be busy and might require more time to process EOP command.
 	  SoC can use this Kconfig to send EOP earlier by itself.
 
+config SOC_INTEL_CSE_SEND_EOP_LATE
+	bool
+	depends on SOC_INTEL_COMMON_BLOCK_CSE
+	help
+	  Use this config to send End Of Post (EOP) late (even after CSE `final` operation)
+	  using boot state either `BS_PAYLOAD_BOOT` or `BS_PAYLOAD_LOAD` from common code
+	  in order to reduce time required to send EOP and getting CSE response.
+	  It has been observed that CSE might be busy and might require more time to
+	  process the EOP command.
+	  SoC can use this Kconfig to send EOP later by itself.
+	  Starting with Jasper Lake, coreboot sends EOP before loading payload hence, this
+	  config is applicable for those platforms.
+
 config SOC_INTEL_CSE_LITE_SKU
 	bool
 	default n
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index e7b486be04..183657445d 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -60,6 +60,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_FSP_RESET
 	select SOC_INTEL_COMMON_PCH_CLIENT
 	select SOC_INTEL_COMMON_RESET
+	select SOC_INTEL_CSE_SEND_EOP_LATE
 	select SOC_INTEL_CSE_SET_EOP
 	select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
 	select SSE2
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 4d87192922..bcf4a82655 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -80,6 +80,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_PCH_CLIENT
 	select SOC_INTEL_COMMON_RESET
 	select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
+	select SOC_INTEL_CSE_SEND_EOP_LATE
 	select SOC_INTEL_CSE_SET_EOP
 	select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
 	select SSE2