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authorFelix Singer <felixsinger@posteo.net>2020-12-06 11:32:25 +0100
committerMichael Niewöhner <foss@mniewoehner.de>2020-12-08 20:50:13 +0000
commitbd7020d68cca2d64869e9fd59cfcb125d80589ad (patch)
treefc0a80db200be476b3413d81bf03a2577e255d85 /src/soc
parentad50856719b923199cdb4f21399a739d66e9319b (diff)
soc/intel/skylake: Restore alphabetical order of Kconfig selects
Built clevo/n130wu with BUILD_TIMELESS=1, coreboot.rom remains identical. Change-Id: I6a5c694a9686a5435aa5c64647286a6017f9aa13 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48376 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/skylake/Kconfig8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 314a08bc82..3eae5f8ff5 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -30,20 +30,20 @@ config CPU_SPECIFIC_OPTIONS
select GENERIC_GPIO_LIB
select HAVE_FSP_GOP
select HAVE_FSP_LOGO_SUPPORT
- select INTEL_DESCRIPTOR_MODE_CAPABLE
+ select HAVE_INTEL_FSP_REPO
select HAVE_SMI_HANDLER
+ select INTEL_DESCRIPTOR_MODE_CAPABLE
select INTEL_GMA_ACPI
select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
- select HAVE_INTEL_FSP_REPO
select IOAPIC
select MRC_SETTINGS_PROTECT
select PARALLEL_MP
select PARALLEL_MP_AP_WORK
select PLATFORM_USES_FSP2_0
- select REG_SCRIPT
- select SA_ENABLE_DPR
select PM_ACPI_TIMER_OPTIONAL
select PMC_GLOBAL_RESET_ENABLE_LOCK
+ select REG_SCRIPT
+ select SA_ENABLE_DPR
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK