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| author | Furquan Shaikh <furquan@google.com> | 2020-11-22 15:45:54 -0800 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-12-09 14:22:58 +0000 |
| commit | ba75c4cc499ec6ac972116a78ab03d8a0d0cc5de (patch) | |
| tree | 63b5d08dfa7145d70b29b3fdef26fa44b61a8500 /src/soc | |
| parent | f078ce1e46bc0a9aa8e895ce6f06f7ff9a9ecf81 (diff) | |
soc/intel/tigerlake: Enable support for extended BIOS window
This change enables support for extended BIOS window by selecting
FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW and providing base and size of the
extended window in host address space.
BUG=b:171534504
Cq-Depend: chromium:2566231
Change-Id: I039155506380310cf867f5f8c5542278be40838a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/tigerlake/Kconfig | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index b97b92e46d..9340cb7385 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -15,6 +15,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_SUPPORTS_PM_TIMER_EMULATION select DRIVERS_USB_ACPI + select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 @@ -101,6 +102,12 @@ config CHIPSET_DEVICETREE string default "soc/intel/tigerlake/chipset.cb" +config EXT_BIOS_WIN_BASE + default 0xf8000000 + +config EXT_BIOS_WIN_SIZE + default 0x2000000 + config IFD_CHIPSET string default "tgl" |