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authorFelix Held <felix-coreboot@felixheld.de>2021-11-09 00:16:19 +0100
committerFelix Held <felix-coreboot@felixheld.de>2021-11-09 23:20:55 +0000
commitb455dd3486a7b2e0b8d98c907cb9389c8283faff (patch)
tree5aab030df934195c12962afcd25520a2fa935a8e /src/soc
parent90d79a751b1c85f436ceb77f39cbeab4c8068b36 (diff)
soc/amd/cezanne,picasso/include/southbridge: fix typo in define
In both the Picasso PPR (rev 3.16) and the Cezanne PPR (rev 3.03) bit 16 of the misc I2C pad control registers is defined as BiasCrtEn, so rename I2C_PAD_CTRL_BIOS_CRT_EN to I2C_PAD_CTRL_BIAS_CRT_EN. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If39ac17a433cb90c944fdde038cd246a995e193a Reviewed-on: https://review.coreboot.org/c/coreboot/+/59028 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/cezanne/include/soc/southbridge.h2
-rw-r--r--src/soc/amd/picasso/include/soc/southbridge.h2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h
index addb850621..1e3697bd59 100644
--- a/src/soc/amd/cezanne/include/soc/southbridge.h
+++ b/src/soc/amd/cezanne/include/soc/southbridge.h
@@ -118,7 +118,7 @@
#define I2C_PAD_CTRL_CAP_UP BIT(13)
#define I2C_PAD_CTRL_RES_DOWN BIT(14)
#define I2C_PAD_CTRL_RES_UP BIT(15)
-#define I2C_PAD_CTRL_BIOS_CRT_EN BIT(16)
+#define I2C_PAD_CTRL_BIAS_CRT_EN BIT(16)
#define I2C_PAD_CTRL_SPARE0 BIT(17)
#define I2C_PAD_CTRL_SPARE1 BIT(18)
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index f547f860a8..300f458fa7 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -115,7 +115,7 @@
#define I2C_PAD_CTRL_CAP_UP BIT(13)
#define I2C_PAD_CTRL_RES_DOWN BIT(14)
#define I2C_PAD_CTRL_RES_UP BIT(15)
-#define I2C_PAD_CTRL_BIOS_CRT_EN BIT(16)
+#define I2C_PAD_CTRL_BIAS_CRT_EN BIT(16)
#define I2C_PAD_CTRL_SPARE0 BIT(17)
#define I2C_PAD_CTRL_SPARE1 BIT(18)