baytrail: Enable panel and set timings

These need to be set before the kernel will work without
running the VBIOS option rom.

Also necessary is setting the PP_CONTROL register with
the EDP_FORCE_VDD bit.

BUG=chrome-os-partner:24367
BRANCH=none
TEST=boot on rambi in normal mode and see the panel come up

Change-Id: I495f818d581d08b80db11785fe28b601ec956b3b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179364
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5000
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)

3 files changed, 116 insertions, 0 deletions

diff --git a/src/soc/intel/baytrail/baytrail/gfx.h b/src/soc/intel/baytrail/baytrail/gfx.h
index 655615d37c..7047dd5a6a 100644
--- a/src/soc/intel/baytrail/baytrail/gfx.h
+++ b/src/soc/intel/baytrail/baytrail/gfx.h
@@ -45,4 +45,20 @@
 #define  APERTURE_SIZE_256MB	(1 << 1)
 #define  APERTURE_SIZE_512MB	(3 << 1)
 
+#define VLV_DISPLAY_BASE	0x180000
+#define PIPEA_REG(reg)		(VLV_DISPLAY_BASE + (reg))
+#define PIPEB_REG(reg)		(VLV_DISPLAY_BASE + 0x100 + (reg))
+
+/* Panel control registers */
+#define HOTPLUG_CTRL		0x61110
+#define PP_CONTROL		0x61204
+#define  PP_CONTROL_UNLOCK		0xabcd0000
+#define  PP_CONTROL_EDP_FORCE_VDD	(1 << 3)
+#define PP_ON_DELAYS		0x61208
+#define PP_OFF_DELAYS		0x6120c
+#define PP_DIVISOR		0x61210
+#define BACKLIGHT_CTL2		0x61250
+#define  BACKLIGHT_ENABLE		(1 << 31)
+#define BACKLIGHT_CTL		0x61254
+
 #endif /* _BAYTRAIL_GFX_H_ */
diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h
index 43a3efb650..2cc3fd65e3 100644
--- a/src/soc/intel/baytrail/chip.h
+++ b/src/soc/intel/baytrail/chip.h
@@ -55,6 +55,31 @@ struct soc_intel_baytrail_config {
 	/* Native SD Card controller - override controller capabilities. */
 	uint32_t sdcard_cap_low;
 	uint32_t sdcard_cap_high;
+
+	/*
+	 * Digital Port Hotplug Enable:
+	 *  0x04 = Enabled, 2ms short pulse
+	 *  0x05 = Enabled, 4.5ms short pulse
+	 *  0x06 = Enabled, 6ms short pulse
+	 *  0x07 = Enabled, 100ms short pulse
+	 */
+	int gpu_pipea_hotplug;
+	int gpu_pipea_port_select;	/* Port select: 1=DP_B 2=DP_C */
+	uint16_t gpu_pipea_power_on_delay;
+	uint16_t gpu_pipea_light_on_delay;
+	uint16_t gpu_pipea_power_off_delay;
+	uint16_t gpu_pipea_light_off_delay;
+	uint16_t gpu_pipea_power_cycle_delay;
+	uint32_t gpu_pipea_backlight_pwm;
+
+	int gpu_pipeb_hotplug;
+	int gpu_pipeb_port_select;	/* Port select: 1=DP_B 2=DP_C */
+	uint16_t gpu_pipeb_power_on_delay;
+	uint16_t gpu_pipeb_light_on_delay;
+	uint16_t gpu_pipeb_power_off_delay;
+	uint16_t gpu_pipeb_light_off_delay;
+	uint16_t gpu_pipeb_power_cycle_delay;
+	uint32_t gpu_pipeb_backlight_pwm;
 };
 
 extern struct chip_operations soc_intel_baytrail_ops;
diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c
index 28b73d5b0b..d2a8ba5d2e 100644
--- a/src/soc/intel/baytrail/gfx.c
+++ b/src/soc/intel/baytrail/gfx.c
@@ -30,6 +30,8 @@
 #include <baytrail/pci_devs.h>
 #include <baytrail/ramstage.h>
 
+#include "chip.h"
+
 #define GFX_TIMEOUT 100000 /* 100ms */
 
 /*
@@ -288,6 +290,77 @@ static void gfx_post_vbios_init(device_t dev)
 	gfx_run_script(dev, gfx_post_vbios_script);
 }
 
+static void gfx_panel_setup(device_t dev)
+{
+	struct soc_intel_baytrail_config *config = dev->chip_info;
+	struct reg_script gfx_pipea_init[] = {
+		REG_SCRIPT_SET_DEV(dev),
+		/* CONTROL */
+		REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_CONTROL),
+				PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD),
+		/* HOTPLUG */
+		REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(HOTPLUG_CTRL),
+				0x1 | (config->gpu_pipea_hotplug << 2)),
+		/* POWER ON */
+		REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_ON_DELAYS),
+				(config->gpu_pipea_port_select << 30 |
+				 config->gpu_pipea_power_on_delay << 16 |
+				 config->gpu_pipea_light_on_delay)),
+		/* POWER OFF */
+		REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_OFF_DELAYS),
+				(config->gpu_pipea_power_off_delay << 16 |
+				 config->gpu_pipea_light_off_delay)),
+		/* DIVISOR */
+		REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_DIVISOR),
+			      ~0x1f, config->gpu_pipea_power_cycle_delay),
+		/* BACKLIGHT */
+		REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(BACKLIGHT_CTL),
+				(config->gpu_pipea_backlight_pwm << 16) |
+				(config->gpu_pipea_backlight_pwm >> 1)),
+		REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(BACKLIGHT_CTL2),
+				BACKLIGHT_ENABLE),
+		REG_SCRIPT_END
+	};
+	struct reg_script gfx_pipeb_init[] = {
+		REG_SCRIPT_SET_DEV(dev),
+		/* CONTROL */
+		REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_CONTROL),
+				PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD),
+		/* HOTPLUG */
+		REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(HOTPLUG_CTRL),
+				0x1 | (config->gpu_pipeb_hotplug << 2)),
+		/* POWER ON */
+		REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_ON_DELAYS),
+				(config->gpu_pipeb_port_select << 30 |
+				 config->gpu_pipeb_power_on_delay << 16 |
+				 config->gpu_pipeb_light_on_delay)),
+		/* POWER OFF */
+		REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_OFF_DELAYS),
+				(config->gpu_pipeb_power_off_delay << 16 |
+				 config->gpu_pipeb_light_off_delay)),
+		/* DIVISOR */
+		REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_DIVISOR),
+			      ~0x1f, config->gpu_pipeb_power_cycle_delay),
+		/* BACKLIGHT */
+		REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(BACKLIGHT_CTL),
+				(config->gpu_pipeb_backlight_pwm << 16) |
+				(config->gpu_pipeb_backlight_pwm >> 1)),
+		REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(BACKLIGHT_CTL2),
+				BACKLIGHT_ENABLE),
+		REG_SCRIPT_END
+	};
+
+	if (config->gpu_pipea_port_select) {
+		printk(BIOS_INFO, "GFX: Initialize PIPEA\n");
+		reg_script_run(gfx_pipea_init);
+	}
+
+	if (config->gpu_pipeb_port_select) {
+		printk(BIOS_INFO, "GFX: Initialize PIPEB\n");
+		reg_script_run(gfx_pipeb_init);
+	}
+}
+
 static void gfx_init(device_t dev)
 {
 	/* Pre VBIOS Init */
@@ -296,6 +369,8 @@ static void gfx_init(device_t dev)
 	/* Power Management Init */
 	gfx_pm_init(dev);
 
+	gfx_panel_setup(dev);
+
 	/* Run VBIOS */
 	pci_dev_init(dev);