soc/intel/cannonlake: Add IGD Support and pre-OS display code

1. Add IGD opregion initialization.
2. Use frame buffer return by FSP for display.
3. Derived from "src/soc/intel/apollolake/graphics.c" with changes
   needed for CNL.

TEST=Pre-OS screen comes up and VBT is getting passed to kernel.

Change-Id: I19c0cf6cfc03fc9df9e98c75af4e486cb5a19e32
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Reviewed-on: https://review.coreboot.org/21999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

3 files changed, 81 insertions, 0 deletions

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 3ce8776cc7..00aa6e9ac8 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -25,6 +25,7 @@ config CPU_SPECIFIC_OPTIONS
 	select HAVE_MONOTONIC_TIMER
 	select HAVE_SMI_HANDLER
 	select INTEL_CAR_NEM_ENHANCED
+	select INTEL_GMA_ACPI
 	select INTEL_GMA_ADD_VBT_DATA_FILE if RUN_FSP_GOP
 	select IOAPIC
 	select MRC_SETTINGS_PROTECT
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index 1076e10efe..8dfff91544 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -32,6 +32,7 @@ ramstage-y += chip.c
 ramstage-y += cpu.c
 ramstage-y += finalize.c
 ramstage-y += gpio.c
+ramstage-y += graphics.c
 ramstage-y += gspi.c
 ramstage-y += gpio.c
 ramstage-y += lpc.c
diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c
new file mode 100644
index 0000000000..a177127da4
--- /dev/null
+++ b/src/soc/intel/cannonlake/graphics.c
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016-2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <console/console.h>
+#include <fsp/util.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <soc/pci_devs.h>
+#include <drivers/intel/gma/opregion.h>
+
+uintptr_t fsp_soc_get_igd_bar(void)
+{
+	device_t dev = SA_DEV_IGD;
+
+	/* Check if IGD PCI device is disabled */
+	if (!dev->enabled)
+		return 0;
+
+	return find_resource(dev, PCI_BASE_ADDRESS_2)->base;
+}
+
+static unsigned long igd_write_opregion(device_t dev, unsigned long current,
+				struct acpi_rsdp *rsdp)
+{
+	igd_opregion_t *opregion;
+
+	printk(BIOS_DEBUG, "ACPI:    * IGD OpRegion\n");
+	opregion = (igd_opregion_t *)current;
+
+	if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
+		return current;
+
+	current += sizeof(igd_opregion_t);
+
+	return acpi_align_current(current);
+}
+
+static const struct device_operations igd_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = pci_dev_init,
+	.write_acpi_tables = igd_write_opregion,
+	.enable           = DEVICE_NOOP
+};
+
+static const unsigned short pci_device_ids[] = {
+	PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_1,
+	PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_2,
+	PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_3,
+	PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_4,
+	PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_1,
+	PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_2,
+	PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3,
+	PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4,
+	0,
+};
+
+static const struct pci_driver integrated_graphics_driver __pci_driver = {
+	.ops		= &igd_ops,
+	.vendor		= PCI_VENDOR_ID_INTEL,
+	.devices	= pci_device_ids,
+};