diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2022-02-03 15:44:48 -0700 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2022-02-08 16:18:31 +0000 |
| commit | af382a77d719ac7e2407c8f47376706a00d32c80 (patch) | |
| tree | 0788ae9aa311a89ce2ce3a182d6ce983246fea5a /src/soc | |
| parent | 2aa5618871d9e558650e33d7911d43daad6019a4 (diff) | |
soc/amd/sabrina/psp_verstage: Implement get_uart_base
The Sabrina PSP doesn't support mapping the UART, so add a dummy
function to return NULL.
BUG=b:215599230
TEST=None
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Idad8e4874e78bb96730feecb5a7b17334d12217c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/sabrina/psp_verstage/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/amd/sabrina/psp_verstage/uart.c | 11 |
2 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/amd/sabrina/psp_verstage/Makefile.inc b/src/soc/amd/sabrina/psp_verstage/Makefile.inc index 27539dafbc..2338bf5e47 100644 --- a/src/soc/amd/sabrina/psp_verstage/Makefile.inc +++ b/src/soc/amd/sabrina/psp_verstage/Makefile.inc @@ -11,6 +11,7 @@ subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../../common/psp_verstage verstage-y += svc.c verstage-y += chipset.c +verstage-y += uart.c verstage-y += $(top)/src/vendorcode/amd/fsp/sabrina/bl_uapp/bl_uapp_startup.S verstage-y += $(top)/src/vendorcode/amd/fsp/sabrina/bl_uapp/bl_uapp_end.S diff --git a/src/soc/amd/sabrina/psp_verstage/uart.c b/src/soc/amd/sabrina/psp_verstage/uart.c new file mode 100644 index 0000000000..1c89f10c99 --- /dev/null +++ b/src/soc/amd/sabrina/psp_verstage/uart.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bl_uapp/bl_syscall_public.h> +#include <amdblocks/uart.h> +#include <types.h> + +uintptr_t get_uart_base(unsigned int idx) +{ + /* Mapping the UART is not supported. */ + return 0; +} |