diff options
| author | Yu-Ping Wu <yupingso@chromium.org> | 2024-07-23 15:29:21 +0800 |
|---|---|---|
| committer | Yu-Ping Wu <yupingso@google.com> | 2024-07-25 03:29:52 +0000 |
| commit | adac4af1763b3258f68e57784ef7f5ee34c04e6a (patch) | |
| tree | 75dcac43f3e1b86cfc11f8d2731b2f63fd8fc5c2 /src/soc | |
| parent | 8cb97d804ee31e18a7b929914811887c432f1505 (diff) | |
soc/amd/psp_verstage: Add -Oz flag for clang
When we tried to add CMOS support to PSP verstage (CB:83495), the clang
builds failed on boards with cezanne SoC (such as Guybrush), due to
over-sized verstage. On the other hand, there is no such problem for gcc
builds on the same boards.
Building PSP verstage by clang generates much larger verstage size (81K)
compared with using gcc (67K). To unblock adding features to verstage,
temporarily enable -Oz for clang builds.
Change-Id: I033458556986ade88fb8e68499b632deae4dd419
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/common/psp_verstage/Makefile.mk | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/amd/common/psp_verstage/Makefile.mk b/src/soc/amd/common/psp_verstage/Makefile.mk index ee71d9930e..9a2cd8196e 100644 --- a/src/soc/amd/common/psp_verstage/Makefile.mk +++ b/src/soc/amd/common/psp_verstage/Makefile.mk @@ -9,6 +9,9 @@ ifeq ($(CONFIG_COMPILER_GCC),y) CFLAGS_arm += -Wstack-usage=40960 else CFLAGS_arm += -Wframe-larger-than=40960 +# Cezanne only has 148KB SRAM for PSP verstage. +# Add -Oz to reduce the verstage size for clang. +CFLAGS_arm += -Oz endif verstage-y += boot_dev.c |