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authorWerner Zeh <werner.zeh@siemens.com>2022-12-22 11:05:17 +0100
committerEric Lai <eric_lai@quanta.corp-partner.google.com>2023-01-10 00:30:47 +0000
commit921bb34c919a617706f269b89333b5dede59880f (patch)
treeacaca2867a0f1ab0fc8510ee5fbfc42b926aa1fd /src/soc
parentfc84ae7aa3cf7e8000ef69f854281f4648eeb2b8 (diff)
soc/intel/elkhartlake: Make SATA speed limit configurable
In cases where there are limitations on the mainboard it can be necessary to limit the used SATA speed even though both, the SATA controller and disk drive support a higher speed rate. The FSP parameter 'SataSpeedLimit' allows to set the speed limit. This patch provides a chip config so that this FSP parameter can be set as needed in the devicetree on mainboard level. Change-Id: I610263b34b0947378d2025211ece4a9ec8fbfef6 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71229 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/elkhartlake/chip.h8
-rw-r--r--src/soc/intel/elkhartlake/fsp_params.c1
2 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h
index 94a2cdff78..d419027478 100644
--- a/src/soc/intel/elkhartlake/chip.h
+++ b/src/soc/intel/elkhartlake/chip.h
@@ -103,6 +103,13 @@ enum fivr_supported_voltage {
FIVR_VOLTAGE_MIN_RETENTION,
};
+/* SATA speed limit */
+enum sata_speed_limit {
+ SATA_DEFAULT = 0,
+ SATA_GEN1,
+ SATA_GEN2
+};
+
struct soc_intel_elkhartlake_config {
/* Common struct containing soc config data required by common code */
@@ -181,6 +188,7 @@ struct soc_intel_elkhartlake_config {
uint8_t SataSalpSupport;
uint8_t SataPortsEnable[CONFIG_MAX_SATA_PORTS];
uint8_t SataPortsDevSlp[CONFIG_MAX_SATA_PORTS];
+ enum sata_speed_limit SataSpeed;
/*
* Enable(0)/Disable(1) SATA Power Optimizer on PCH side.
* Default 0. Setting this to 1 disables the SATA Power Optimizer.
diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c
index c72d4da2b1..1466ee21a2 100644
--- a/src/soc/intel/elkhartlake/fsp_params.c
+++ b/src/soc/intel/elkhartlake/fsp_params.c
@@ -368,6 +368,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->SataMode = config->SataMode;
params->SataSalpSupport = config->SataSalpSupport;
params->SataPwrOptEnable = !(config->SataPwrOptimizeDisable);
+ params->SataSpeedLimit = config->SataSpeed;
for (i = 0; i < CONFIG_MAX_SATA_PORTS; i++) {
params->SataPortsEnable[i] = config->SataPortsEnable[i];